BE797619A - Systeme perfectionne de traitement de donnes - Google Patents

Systeme perfectionne de traitement de donnes

Info

Publication number
BE797619A
BE797619A BE129522A BE129522A BE797619A BE 797619 A BE797619 A BE 797619A BE 129522 A BE129522 A BE 129522A BE 129522 A BE129522 A BE 129522A BE 797619 A BE797619 A BE 797619A
Authority
BE
Belgium
Prior art keywords
data processing
processing system
perfected
perfected data
processing
Prior art date
Application number
BE129522A
Other languages
English (en)
French (fr)
Inventor
L Censier
A M Recoque
Original Assignee
Comp Int
Information
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Comp Int, Information filed Critical Comp Int
Publication of BE797619A publication Critical patent/BE797619A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1633—Error detection by comparing the output of redundant processing systems using mutual exchange of the output between the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
BE129522A 1972-04-24 1973-03-30 Systeme perfectionne de traitement de donnes BE797619A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7214418A FR2182259A5 (de) 1972-04-24 1972-04-24

Publications (1)

Publication Number Publication Date
BE797619A true BE797619A (fr) 1973-07-16

Family

ID=9097394

Family Applications (1)

Application Number Title Priority Date Filing Date
BE129522A BE797619A (fr) 1972-04-24 1973-03-30 Systeme perfectionne de traitement de donnes

Country Status (10)

Country Link
US (1) US4012717A (de)
JP (1) JPS5247980B2 (de)
BE (1) BE797619A (de)
BR (1) BR7302852D0 (de)
DE (1) DE2319753B2 (de)
ES (1) ES414009A1 (de)
FR (1) FR2182259A5 (de)
GB (1) GB1414095A (de)
IT (1) IT980879B (de)
NL (1) NL159799B (de)

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US4679151A (en) * 1982-07-20 1987-07-07 Lucas Industries Public Limited Company Control for a limiting device
US4573174A (en) * 1982-09-07 1986-02-25 Pitney Bowes Inc. Electronic postage meter having interlock between mechanical and electrical registers
DE3412049A1 (de) * 1984-03-30 1985-10-17 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Signaltechnisch sichere datenverarbeitungseinrichtung
AU568977B2 (en) * 1985-05-10 1988-01-14 Tandem Computers Inc. Dual processor error detection system
US4736339A (en) * 1985-12-16 1988-04-05 Gte Communication Systems Corporation Circuit for simplex I/O terminal control by duplex processors
US4792955A (en) * 1986-08-21 1988-12-20 Intel Corporation Apparatus for on-line checking and reconfiguration of integrated circuit chips
DE3639055C2 (de) * 1986-11-14 1998-02-05 Bosch Gmbh Robert Verfahren zur Betriebsüberwachung und Fehlerkorrektur von Rechnern eines Mehrrechnersystems und Mehrrechnersystem
DE3642851A1 (de) * 1986-12-16 1988-06-30 Bbc Brown Boveri & Cie Fehlertolerantes rechensystem und verfahren zum erkennen, lokalisieren und eliminieren von fehlerhaften einheiten in einem solchen system
US5079740A (en) * 1987-01-12 1992-01-07 Ncr Corporation System and method of providing an automatic back-up primary terminal for a cluster of secondary terminals
US4907228A (en) * 1987-09-04 1990-03-06 Digital Equipment Corporation Dual-rail processor with error checking at single rail interfaces
EP0306244B1 (de) * 1987-09-04 1995-06-21 Digital Equipment Corporation Fehlertolerantes Rechnersystem mit Fehler-Eingrenzung
EP0306211A3 (de) * 1987-09-04 1990-09-26 Digital Equipment Corporation Synchronisiertes Doppelrechnersystem
US5185877A (en) * 1987-09-04 1993-02-09 Digital Equipment Corporation Protocol for transfer of DMA data
US4916704A (en) * 1987-09-04 1990-04-10 Digital Equipment Corporation Interface of non-fault tolerant components to fault tolerant system
CA1320276C (en) * 1987-09-04 1993-07-13 William F. Bruckert Dual rail processors with error checking on i/o reads
GB8729901D0 (en) * 1987-12-22 1988-02-03 Lucas Ind Plc Dual computer cross-checking system
US4873631A (en) * 1988-04-25 1989-10-10 Ncr Corporation Point of sale automatic back-up system and method
US4903270A (en) * 1988-06-14 1990-02-20 Intel Corporation Apparatus for self checking of functional redundancy check (FRC) logic
JP2722579B2 (ja) * 1988-12-19 1998-03-04 株式会社明電舎 無停電電源装置並列冗長システムの保護装置
JPH07117905B2 (ja) * 1989-02-09 1995-12-18 日本電気株式会社 マイクロプロセッサ
US5086499A (en) * 1989-05-23 1992-02-04 Aeg Westinghouse Transportation Systems, Inc. Computer network for real time control with automatic fault identification and by-pass
US5163138A (en) * 1989-08-01 1992-11-10 Digital Equipment Corporation Protocol for read write transfers via switching logic by transmitting and retransmitting an address
US5068780A (en) * 1989-08-01 1991-11-26 Digital Equipment Corporation Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones
US5251227A (en) * 1989-08-01 1993-10-05 Digital Equipment Corporation Targeted resets in a data processor including a trace memory to store transactions
US5153881A (en) * 1989-08-01 1992-10-06 Digital Equipment Corporation Method of handling errors in software
EP0415545B1 (de) * 1989-08-01 1996-06-19 Digital Equipment Corporation Verfahren zur Softwarefehlerbehandlung
US5048022A (en) * 1989-08-01 1991-09-10 Digital Equipment Corporation Memory device with transfer of ECC signals on time division multiplexed bidirectional lines
US5065312A (en) * 1989-08-01 1991-11-12 Digital Equipment Corporation Method of converting unique data to system data
US5068851A (en) * 1989-08-01 1991-11-26 Digital Equipment Corporation Apparatus and method for documenting faults in computing modules
DE69325769T2 (de) * 1992-11-04 2000-03-23 Digital Equipment Corp., Maynard Erkennung von Befehlssynchronisationsfehlern
US5838894A (en) 1992-12-17 1998-11-17 Tandem Computers Incorporated Logical, fail-functional, dual central processor units formed from three processor units
US5751932A (en) * 1992-12-17 1998-05-12 Tandem Computers Incorporated Fail-fast, fail-functional, fault-tolerant multiprocessor system
US5835953A (en) * 1994-10-13 1998-11-10 Vinca Corporation Backup system that takes a snapshot of the locations in a mass storage device that has been identified for updating prior to updating
US5649152A (en) * 1994-10-13 1997-07-15 Vinca Corporation Method and system for providing a static snapshot of data stored on a mass storage system
JP3132744B2 (ja) * 1995-05-24 2001-02-05 株式会社日立製作所 二重化ｃｐｕ保守交換時の動作一致検証方式
WO2001073969A1 (de) * 2000-03-24 2001-10-04 Siemens Aktiengesellschaft Verfahren zur ersatzschaltung eines baugruppenfeldes in digitalen systemen zur datenübertragung und ersatzschaltung zur durchführung des verfahrens
US7194671B2 (en) * 2001-12-31 2007-03-20 Intel Corporation Mechanism handling race conditions in FRC-enabled processors
US6954886B2 (en) * 2001-12-31 2005-10-11 Intel Corporation Deterministic hardware reset for FRC machine
US7055060B2 (en) * 2002-12-19 2006-05-30 Intel Corporation On-die mechanism for high-reliability processor

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US3303474A (en) * 1963-01-17 1967-02-07 Rca Corp Duplexing system for controlling online and standby conditions of two computers
US3409877A (en) * 1964-11-27 1968-11-05 Bell Telephone Labor Inc Automatic maintenance arrangement for data processing systems
DE1524239B2 (de) * 1965-11-16 1971-07-22 Telefonaktiebolaget Lm Ericsson, Stockholm Schaltungsanordnung zur aufrechterhaltung eines fehler freien betriebes bei einer rechenanlage mit mindestens zwei parallel arbeitenden rechengeraeten
US3471686A (en) * 1966-01-03 1969-10-07 Bell Telephone Labor Inc Error detection system for synchronized duplicate data processing units
US3444528A (en) * 1966-11-17 1969-05-13 Martin Marietta Corp Redundant computer systems
US3517171A (en) * 1967-10-30 1970-06-23 Nasa Self-testing and repairing computer
US3544777A (en) * 1967-11-06 1970-12-01 Trw Inc Two memory self-correcting system
US3623011A (en) * 1969-06-25 1971-11-23 Bell Telephone Labor Inc Time-shared access to computer registers
US3770948A (en) * 1972-05-26 1973-11-06 Gte Automatic Electric Lab Inc Data handling system maintenance arrangement

Also Published As

Publication number Publication date
IT980879B (it) 1974-10-10
FR2182259A5 (de) 1973-12-07
DE2319753A1 (de) 1973-11-08
NL159799B (nl) 1979-03-15
ES414009A1 (es) 1976-02-01
GB1414095A (en) 1975-11-19
JPS4955248A (de) 1974-05-29
US4012717A (en) 1977-03-15
NL7305686A (de) 1973-10-26
BR7302852D0 (pt) 1974-07-11
JPS5247980B2 (de) 1977-12-06
DE2319753B2 (de) 1979-10-31

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: S.A. CIE INTERNATIONALE POUR L' INFORMATIQUE

Effective date: 19860331