BE730645A - - Google Patents
Info
- Publication number
- BE730645A BE730645A BE730645DA BE730645A BE 730645 A BE730645 A BE 730645A BE 730645D A BE730645D A BE 730645DA BE 730645 A BE730645 A BE 730645A
- Authority
- BE
- Belgium
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/145—Shaped junctions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/151—Simultaneous diffusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/173—Washed emitter
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR147642 | 1968-04-10 | ||
| FR151075A FR95067E (fr) | 1968-04-10 | 1968-05-08 | Procédé de fabrication de dispositifs semi-conducteurs. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BE730645A true BE730645A (en:Method) | 1969-09-29 |
Family
ID=26181939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BE730645D BE730645A (en:Method) | 1968-04-10 | 1969-03-28 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3635772A (en:Method) |
| BE (1) | BE730645A (en:Method) |
| CH (1) | CH499205A (en:Method) |
| DE (1) | DE1918054A1 (en:Method) |
| FR (2) | FR1569872A (en:Method) |
| GB (1) | GB1218676A (en:Method) |
| NL (1) | NL6904936A (en:Method) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BE759583A (fr) * | 1970-02-20 | 1971-04-30 | Rca Corp | Transistor de puissance pour micro-ondes |
| US3860461A (en) * | 1973-05-29 | 1975-01-14 | Texas Instruments Inc | Method for fabricating semiconductor devices utilizing composite masking |
| US3922184A (en) * | 1973-12-26 | 1975-11-25 | Ibm | Method for forming openings through insulative layers in the fabrication of integrated circuits |
| DE2453134C3 (de) * | 1974-11-08 | 1983-02-10 | Deutsche Itt Industries Gmbh, 7800 Freiburg | Planardiffusionsverfahren |
| JPS543479A (en) * | 1977-06-09 | 1979-01-11 | Toshiba Corp | Semiconductor device and its manufacture |
| JPS6410951B2 (en:Method) * | 1979-12-28 | 1989-02-22 | Intaanashonaru Bijinesu Mashiinzu Corp | |
| JPS5955054A (ja) * | 1982-09-24 | 1984-03-29 | Hitachi Ltd | 半導体装置の製造方法 |
| JPS60175453A (ja) * | 1984-02-20 | 1985-09-09 | Matsushita Electronics Corp | トランジスタの製造方法 |
| US4883767A (en) * | 1986-12-05 | 1989-11-28 | General Electric Company | Method of fabricating self aligned semiconductor devices |
| US5010034A (en) * | 1989-03-07 | 1991-04-23 | National Semiconductor Corporation | CMOS and bipolar fabrication process using selective epitaxial growth scalable to below 0.5 micron |
| US6399465B1 (en) * | 2000-02-24 | 2002-06-04 | United Microelectronics Corp. | Method for forming a triple well structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3342650A (en) * | 1964-02-10 | 1967-09-19 | Hitachi Ltd | Method of making semiconductor devices by double masking |
-
1968
- 1968-04-10 FR FR147642A patent/FR1569872A/fr not_active Expired
- 1968-05-08 FR FR151075A patent/FR95067E/fr not_active Expired
-
1969
- 1969-03-28 BE BE730645D patent/BE730645A/xx unknown
- 1969-03-31 NL NL6904936A patent/NL6904936A/xx unknown
- 1969-04-09 GB GB08267/69A patent/GB1218676A/en not_active Expired
- 1969-04-09 DE DE19691918054 patent/DE1918054A1/de active Pending
- 1969-04-10 CH CH473569A patent/CH499205A/fr not_active IP Right Cessation
- 1969-04-10 US US815140A patent/US3635772A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CH499205A (fr) | 1970-11-15 |
| US3635772A (en) | 1972-01-18 |
| NL6904936A (en:Method) | 1969-10-14 |
| FR1569872A (en:Method) | 1969-06-06 |
| DE1918054A1 (de) | 1969-10-23 |
| GB1218676A (en) | 1971-01-06 |
| FR95067E (fr) | 1970-06-19 |