AU767325B2 - A method and apparatus for compressing signals in a fixed point format without introducing a bias - Google Patents

A method and apparatus for compressing signals in a fixed point format without introducing a bias Download PDF

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Publication number
AU767325B2
AU767325B2 AU54866/99A AU5486699A AU767325B2 AU 767325 B2 AU767325 B2 AU 767325B2 AU 54866/99 A AU54866/99 A AU 54866/99A AU 5486699 A AU5486699 A AU 5486699A AU 767325 B2 AU767325 B2 AU 767325B2
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AU
Australia
Prior art keywords
signal
bit
bits
output
equal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU54866/99A
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English (en)
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AU5486699A (en
Inventor
Jeffrey A. Levin
Christopher C. Riddle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of AU5486699A publication Critical patent/AU5486699A/en
Application granted granted Critical
Publication of AU767325B2 publication Critical patent/AU767325B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49952—Sticky bit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49963—Rounding to nearest

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
AU54866/99A 1998-08-14 1999-08-13 A method and apparatus for compressing signals in a fixed point format without introducing a bias Ceased AU767325B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/134,248 US6148317A (en) 1998-08-14 1998-08-14 Method and apparatus for compressing signals in a fixed point format without introducing a bias
US09/134248 1998-08-14
PCT/US1999/018546 WO2000010253A2 (en) 1998-08-14 1999-08-13 A method and apparatus for compressing signals in a fixed point format without introducing a bias

Publications (2)

Publication Number Publication Date
AU5486699A AU5486699A (en) 2000-03-06
AU767325B2 true AU767325B2 (en) 2003-11-06

Family

ID=22462453

Family Applications (1)

Application Number Title Priority Date Filing Date
AU54866/99A Ceased AU767325B2 (en) 1998-08-14 1999-08-13 A method and apparatus for compressing signals in a fixed point format without introducing a bias

Country Status (11)

Country Link
US (1) US6148317A (enExample)
EP (1) EP1110325B1 (enExample)
JP (1) JP4354648B2 (enExample)
KR (1) KR20010072504A (enExample)
CN (1) CN1321269A (enExample)
AT (1) ATE270009T1 (enExample)
AU (1) AU767325B2 (enExample)
CA (1) CA2340421A1 (enExample)
DE (1) DE69918313T2 (enExample)
RU (1) RU2233024C2 (enExample)
WO (1) WO2000010253A2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6243728B1 (en) * 1999-07-12 2001-06-05 Sony Corporation Of Japan Partitioned shift right logic circuit having rounding support
GB0031771D0 (en) * 2000-12-29 2001-02-07 Lsi Logic Corp Bit reduction using dither,rounding and error feedback
JP3755602B2 (ja) * 2003-03-04 2006-03-15 ソニー株式会社 信号処理装置、信用処理装置用プログラム、信号処理装置用プログラムを記録した記録媒体、及び信号処理方法
US8301803B2 (en) 2009-10-23 2012-10-30 Samplify Systems, Inc. Block floating point compression of signal data

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992009032A1 (en) * 1990-11-09 1992-05-29 Adaptive Solutions, Inc. Unbiased bit disposal apparatus and method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3199371B2 (ja) * 1990-07-30 2001-08-20 松下電器産業株式会社 丸め装置
US5214598A (en) * 1990-11-09 1993-05-25 Adaptive Solutions, Inc. Unbiased bit disposal apparatus and method
EP0670096A4 (en) * 1992-11-16 1996-03-27 Multimedia Systems Corp METHOD FOR PRODUCING AND TRANSMITTING IMPROVED INTERACTIVE MULTIMEDIA INFORMATION.
US5491516A (en) * 1993-01-14 1996-02-13 Rca Thomson Licensing Corporation Field elimination apparatus for a video compression/decompression system
TW224553B (en) * 1993-03-01 1994-06-01 Sony Co Ltd Method and apparatus for inverse discrete consine transform and coding/decoding of moving picture
US5424967A (en) * 1993-11-29 1995-06-13 Hewlett-Packard Company Shift and rounding circuit and method
US5594660A (en) * 1994-09-30 1997-01-14 Cirrus Logic, Inc. Programmable audio-video synchronization method and apparatus for multimedia systems
US5696710A (en) * 1995-12-29 1997-12-09 Thomson Consumer Electronics, Inc. Apparatus for symmetrically reducing N least significant bits of an M-bit digital signal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992009032A1 (en) * 1990-11-09 1992-05-29 Adaptive Solutions, Inc. Unbiased bit disposal apparatus and method

Also Published As

Publication number Publication date
KR20010072504A (ko) 2001-07-31
JP2002523913A (ja) 2002-07-30
US6148317A (en) 2000-11-14
WO2000010253A3 (en) 2000-05-18
JP4354648B2 (ja) 2009-10-28
AU5486699A (en) 2000-03-06
DE69918313T2 (de) 2005-09-29
CN1321269A (zh) 2001-11-07
ATE270009T1 (de) 2004-07-15
RU2233024C2 (ru) 2004-07-20
EP1110325A2 (en) 2001-06-27
DE69918313D1 (de) 2004-07-29
WO2000010253A2 (en) 2000-02-24
EP1110325B1 (en) 2004-06-23
CA2340421A1 (en) 2000-02-24

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