DE69918313D1 - Verfahren und vorrichtung zur signalkompression im festpunktformat ohne bias - Google Patents

Verfahren und vorrichtung zur signalkompression im festpunktformat ohne bias

Info

Publication number
DE69918313D1
DE69918313D1 DE69918313T DE69918313T DE69918313D1 DE 69918313 D1 DE69918313 D1 DE 69918313D1 DE 69918313 T DE69918313 T DE 69918313T DE 69918313 T DE69918313 T DE 69918313T DE 69918313 D1 DE69918313 D1 DE 69918313D1
Authority
DE
Germany
Prior art keywords
bias
signal
fixed point
rounded
signal compression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69918313T
Other languages
English (en)
Other versions
DE69918313T2 (de
Inventor
C Riddle
A Levin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of DE69918313D1 publication Critical patent/DE69918313D1/de
Application granted granted Critical
Publication of DE69918313T2 publication Critical patent/DE69918313T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49952—Sticky bit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49963—Rounding to nearest

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
DE69918313T 1998-08-14 1999-08-13 Verfahren und vorrichtung zur signalkompression im festpunktformat ohne bias Expired - Fee Related DE69918313T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/134,248 US6148317A (en) 1998-08-14 1998-08-14 Method and apparatus for compressing signals in a fixed point format without introducing a bias
US134248 1998-08-14
PCT/US1999/018546 WO2000010253A2 (en) 1998-08-14 1999-08-13 A method and apparatus for compressing signals in a fixed point format without introducing a bias

Publications (2)

Publication Number Publication Date
DE69918313D1 true DE69918313D1 (de) 2004-07-29
DE69918313T2 DE69918313T2 (de) 2005-09-29

Family

ID=22462453

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69918313T Expired - Fee Related DE69918313T2 (de) 1998-08-14 1999-08-13 Verfahren und vorrichtung zur signalkompression im festpunktformat ohne bias

Country Status (11)

Country Link
US (1) US6148317A (de)
EP (1) EP1110325B1 (de)
JP (1) JP4354648B2 (de)
KR (1) KR20010072504A (de)
CN (1) CN1321269A (de)
AT (1) ATE270009T1 (de)
AU (1) AU767325B2 (de)
CA (1) CA2340421A1 (de)
DE (1) DE69918313T2 (de)
RU (1) RU2233024C2 (de)
WO (1) WO2000010253A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6243728B1 (en) * 1999-07-12 2001-06-05 Sony Corporation Of Japan Partitioned shift right logic circuit having rounding support
GB0031771D0 (en) * 2000-12-29 2001-02-07 Lsi Logic Corp Bit reduction using dither,rounding and error feedback
JP3755602B2 (ja) * 2003-03-04 2006-03-15 ソニー株式会社 信号処理装置、信用処理装置用プログラム、信号処理装置用プログラムを記録した記録媒体、及び信号処理方法
US8301803B2 (en) * 2009-10-23 2012-10-30 Samplify Systems, Inc. Block floating point compression of signal data

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3199371B2 (ja) * 1990-07-30 2001-08-20 松下電器産業株式会社 丸め装置
US5214598A (en) * 1990-11-09 1993-05-25 Adaptive Solutions, Inc. Unbiased bit disposal apparatus and method
JPH05503178A (ja) * 1990-11-09 1993-05-27 アダプティブ・ソリューションズ・インコーポレーテッド 偏りのないビット廃棄装置および方法
US5424967A (en) * 1993-11-29 1995-06-13 Hewlett-Packard Company Shift and rounding circuit and method
US5696710A (en) * 1995-12-29 1997-12-09 Thomson Consumer Electronics, Inc. Apparatus for symmetrically reducing N least significant bits of an M-bit digital signal

Also Published As

Publication number Publication date
ATE270009T1 (de) 2004-07-15
EP1110325A2 (de) 2001-06-27
KR20010072504A (ko) 2001-07-31
WO2000010253A2 (en) 2000-02-24
AU767325B2 (en) 2003-11-06
DE69918313T2 (de) 2005-09-29
US6148317A (en) 2000-11-14
CA2340421A1 (en) 2000-02-24
RU2233024C2 (ru) 2004-07-20
JP2002523913A (ja) 2002-07-30
JP4354648B2 (ja) 2009-10-28
WO2000010253A3 (en) 2000-05-18
CN1321269A (zh) 2001-11-07
EP1110325B1 (de) 2004-06-23
AU5486699A (en) 2000-03-06

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee