AU2003298530A1 - Sublithographic nanoscale memory architecture - Google Patents

Sublithographic nanoscale memory architecture

Info

Publication number
AU2003298530A1
AU2003298530A1 AU2003298530A AU2003298530A AU2003298530A1 AU 2003298530 A1 AU2003298530 A1 AU 2003298530A1 AU 2003298530 A AU2003298530 A AU 2003298530A AU 2003298530 A AU2003298530 A AU 2003298530A AU 2003298530 A1 AU2003298530 A1 AU 2003298530A1
Authority
AU
Australia
Prior art keywords
nanoscale
wires
memory architecture
selecting
nanoscale memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003298530A
Other languages
English (en)
Other versions
AU2003298530A8 (en
Inventor
Andre' Dehon
Charles M. Lieber
Patrick D. Lincoln
John Savage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SRI International Inc
California Institute of Technology
Brown University
Harvard University
Original Assignee
SRI International Inc
California Institute of Technology
Brown University
Harvard University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SRI International Inc, California Institute of Technology, Brown University, Harvard University filed Critical SRI International Inc
Publication of AU2003298530A8 publication Critical patent/AU2003298530A8/xx
Publication of AU2003298530A1 publication Critical patent/AU2003298530A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00Subject matter not provided for in other groups of this subclass
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0023Address circuits or decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G11C13/025Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/10Decoders
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117Shapes of semiconductor bodies
    • H10D62/118Nanostructure semiconductor bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117Shapes of semiconductor bodies
    • H10D62/118Nanostructure semiconductor bodies
    • H10D62/119Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/71Three dimensional array
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/77Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/81Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • H10B20/20Programmable ROM [PROM] devices comprising field-effect components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00Nanotechnology
    • Y10S977/70Nanostructure
    • Y10S977/762Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00Nanotechnology
    • Y10S977/902Specified use of nanostructure
    • Y10S977/932Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/943Information storage or retrieval using nanostructure

Landscapes

  • Engineering & Computer Science (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Micro-Organisms Or Cultivation Processes Thereof (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Magnetic Resonance Imaging Apparatus (AREA)
  • Ropes Or Cables (AREA)
  • Prostheses (AREA)
  • Silicon Compounds (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
AU2003298530A 2002-07-25 2003-07-24 Sublithographic nanoscale memory architecture Abandoned AU2003298530A1 (en)

Applications Claiming Priority (15)

Application Number Priority Date Filing Date Title
US39894302P 2002-07-25 2002-07-25
US60/398,943 2002-07-25
US40039402P 2002-08-01 2002-08-01
US60/400,394 2002-08-01
US41517602P 2002-09-30 2002-09-30
US60/415,176 2002-09-30
US42901002P 2002-11-25 2002-11-25
US60/429,010 2002-11-25
US44199503P 2003-01-23 2003-01-23
US60/441,995 2003-01-23
US46535703P 2003-04-25 2003-04-25
US60/465,357 2003-04-25
US46738803P 2003-05-02 2003-05-02
US60/467,388 2003-05-02
PCT/US2003/023199 WO2004034467A2 (en) 2002-07-25 2003-07-24 Sublithographic nanoscale memory architecture

Publications (2)

Publication Number Publication Date
AU2003298530A8 AU2003298530A8 (en) 2004-05-04
AU2003298530A1 true AU2003298530A1 (en) 2004-05-04

Family

ID=32097212

Family Applications (2)

Application Number Title Priority Date Filing Date
AU2003298530A Abandoned AU2003298530A1 (en) 2002-07-25 2003-07-24 Sublithographic nanoscale memory architecture
AU2003298529A Abandoned AU2003298529A1 (en) 2002-07-25 2003-07-24 Stochastic assembly of sublithographic nanoscale interfaces

Family Applications After (1)

Application Number Title Priority Date Filing Date
AU2003298529A Abandoned AU2003298529A1 (en) 2002-07-25 2003-07-24 Stochastic assembly of sublithographic nanoscale interfaces

Country Status (7)

Country Link
US (2) US6900479B2 (cg-RX-API-DMAC7.html)
EP (3) EP1525586B1 (cg-RX-API-DMAC7.html)
JP (2) JP2005539404A (cg-RX-API-DMAC7.html)
AT (2) ATE360873T1 (cg-RX-API-DMAC7.html)
AU (2) AU2003298530A1 (cg-RX-API-DMAC7.html)
DE (2) DE60325903D1 (cg-RX-API-DMAC7.html)
WO (2) WO2004061859A2 (cg-RX-API-DMAC7.html)

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Also Published As

Publication number Publication date
AU2003298530A8 (en) 2004-05-04
DE60313462D1 (de) 2007-06-06
WO2004034467A3 (en) 2004-08-26
EP1525586B1 (en) 2007-04-25
US6900479B2 (en) 2005-05-31
EP1525586A2 (en) 2005-04-27
WO2004034467A2 (en) 2004-04-22
AU2003298529A1 (en) 2004-07-29
US20040113139A1 (en) 2004-06-17
AU2003298529A8 (en) 2004-07-29
EP1758126A3 (en) 2007-03-14
JP2006512782A (ja) 2006-04-13
US20040113138A1 (en) 2004-06-17
EP1758126A2 (en) 2007-02-28
US6963077B2 (en) 2005-11-08
ATE360873T1 (de) 2007-05-15
WO2004061859A3 (en) 2005-02-03
WO2004061859A2 (en) 2004-07-22
ATE421147T1 (de) 2009-01-15
JP2005539404A (ja) 2005-12-22
DE60325903D1 (de) 2009-03-05
EP1525585A2 (en) 2005-04-27
DE60313462T2 (de) 2008-01-03

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