AU2002331721A1 - Wafer level underfill and interconnect process - Google Patents

Wafer level underfill and interconnect process

Info

Publication number
AU2002331721A1
AU2002331721A1 AU2002331721A AU2002331721A AU2002331721A1 AU 2002331721 A1 AU2002331721 A1 AU 2002331721A1 AU 2002331721 A AU2002331721 A AU 2002331721A AU 2002331721 A AU2002331721 A AU 2002331721A AU 2002331721 A1 AU2002331721 A1 AU 2002331721A1
Authority
AU
Australia
Prior art keywords
wafer level
interconnect process
level underfill
underfill
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002331721A
Inventor
Martin Standing
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Americas Corp
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Publication of AU2002331721A1 publication Critical patent/AU2002331721A1/en
Abandoned legal-status Critical Current

Links

AU2002331721A 2001-08-24 2002-08-21 Wafer level underfill and interconnect process Abandoned AU2002331721A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60/314,818 2001-08-24
US10/225,399 2002-08-20

Publications (1)

Publication Number Publication Date
AU2002331721A1 true AU2002331721A1 (en) 2003-03-10

Family

ID=

Similar Documents

Publication Publication Date Title
AU2002245685A1 (en) Wafer level interposer
AU2002352993A1 (en) Chip and wafer integration process using vertical connections
AU2002249861A1 (en) Wafer level interconnection
EP1361614B8 (en) Semiconductor device manufacturing method
AU2002247383A1 (en) In-street integrated circuit wafer via
GB2373922B (en) CMOS semiconductor device, and method of manufacturing the same
AU2002316979A1 (en) Semiconductor device
AU2002349507A1 (en) Mos semiconductor device
AU2002338003A1 (en) Semiconductor Devices
AU2002349581A1 (en) Semiconductor device and manufacturing method thereof
AU2002330511A1 (en) Semiconductor calculation device
EP1424409A4 (en) Semiconductor wafer and its manufacturing method
AU2001271293A1 (en) Semiconductor structure, device, circuit, and process
AU2002346547A1 (en) Organic semiconductor and method
EP1294023A3 (en) Semiconductor integrated circuit modules, manufacturing methods and usage thereof
AU2002257257A1 (en) Semiconductor structures, devices and method of fabrication
AU2002357256A1 (en) Semiconductor apparatus
AU2002366177A1 (en) Method of forming narrow trenches in semiconductor substrates
AU5926800A (en) Semiconductor devices and process for manufacture
AU2002357591A1 (en) Substrate treating method
AU2003213394A1 (en) Polishing equipment, and method of manufacturing semiconductor device using the equipment
AU2002346886A1 (en) Method and device for drying semiconductor wafers
AU2002331721A1 (en) Wafer level underfill and interconnect process
EP1291132A3 (en) Semiconductor wafer polishing apparatus and polishing method
AU2002303463A1 (en) Semiconductor structures and devices