AU2001267057A1 - Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors - Google Patents

Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors

Info

Publication number
AU2001267057A1
AU2001267057A1 AU2001267057A AU6705701A AU2001267057A1 AU 2001267057 A1 AU2001267057 A1 AU 2001267057A1 AU 2001267057 A AU2001267057 A AU 2001267057A AU 6705701 A AU6705701 A AU 6705701A AU 2001267057 A1 AU2001267057 A1 AU 2001267057A1
Authority
AU
Australia
Prior art keywords
memory operations
dynamic multi
streaming processors
atomicity
implementing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001267057A
Other languages
English (en)
Inventor
Stephen Melvin
Mario D Nemirovsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Clearwater Networks Inc
Original Assignee
Clearwater Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/592,106 external-priority patent/US7257814B1/en
Application filed by Clearwater Networks Inc filed Critical Clearwater Networks Inc
Publication of AU2001267057A1 publication Critical patent/AU2001267057A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Multi Processors (AREA)
AU2001267057A 2000-06-12 2001-06-07 Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors Abandoned AU2001267057A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/592,106 US7257814B1 (en) 1998-12-16 2000-06-12 Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US09592106 2000-06-12
PCT/US2001/040900 WO2001097020A1 (fr) 2000-06-12 2001-06-07 Procede et appareil de mise en oeuvre d'une atomicite d'operations de memoire dans des processeurs multi-flux dynamiques

Publications (1)

Publication Number Publication Date
AU2001267057A1 true AU2001267057A1 (en) 2001-12-24

Family

ID=24369309

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001267057A Abandoned AU2001267057A1 (en) 2000-06-12 2001-06-07 Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors

Country Status (5)

Country Link
EP (1) EP1299801B1 (fr)
JP (1) JP4926364B2 (fr)
AU (1) AU2001267057A1 (fr)
DE (1) DE60143747D1 (fr)
WO (1) WO2001097020A1 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6625698B2 (en) * 2000-12-28 2003-09-23 Unisys Corporation Method and apparatus for controlling memory storage locks based on cache line ownership
IL161107A0 (en) 2001-09-28 2004-08-31 Tidal Networks Inc Multi-threaded packet processing engine for stateful packet processing
US20060218556A1 (en) * 2001-09-28 2006-09-28 Nemirovsky Mario D Mechanism for managing resource locking in a multi-threaded environment
US20040199727A1 (en) * 2003-04-02 2004-10-07 Narad Charles E. Cache allocation
US8281080B2 (en) 2004-09-02 2012-10-02 Freescale Semiconductor, Inc. Method and apparatus for modifying an information unit using an atomic operation
US9207943B2 (en) 2009-03-17 2015-12-08 Qualcomm Incorporated Real time multithreaded scheduler and scheduling method
US8516577B2 (en) * 2010-09-22 2013-08-20 Intel Corporation Regulating atomic memory operations to prevent denial of service attack
JP2012208662A (ja) * 2011-03-29 2012-10-25 Toyota Motor Corp マルチスレッド・プロセッサ
US9465670B2 (en) 2011-12-16 2016-10-11 Intel Corporation Generational thread scheduler using reservations for fair scheduling
CN111796921B (zh) * 2020-06-30 2023-05-30 西安微电子技术研究所 嵌入式多核操作系统调度方法、调度装置、电子设备及存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621260A (en) * 1979-07-27 1981-02-27 Nec Corp Access unit
US5142676A (en) * 1988-12-28 1992-08-25 Gte Laboratories Incorporated Separate content addressable memories for storing locked segment addresses and locking processor identifications for controlling access to shared memory
JPH05225117A (ja) * 1992-02-14 1993-09-03 Nec Corp 主記憶装置の排他制御回路
US5946711A (en) * 1997-05-30 1999-08-31 Oracle Corporation System for locking data in a shared cache
GB9809022D0 (en) * 1998-04-29 1998-06-24 Int Computers Ltd Semaphore for a computer system

Also Published As

Publication number Publication date
EP1299801A4 (fr) 2005-08-24
WO2001097020A1 (fr) 2001-12-20
DE60143747D1 (de) 2011-02-10
EP1299801A1 (fr) 2003-04-09
JP4926364B2 (ja) 2012-05-09
JP2004503864A (ja) 2004-02-05
EP1299801B1 (fr) 2010-12-29

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