AU2001284924A1 - Method and system for using dynamic random access memory as cache memory - Google Patents
Method and system for using dynamic random access memory as cache memoryInfo
- Publication number
- AU2001284924A1 AU2001284924A1 AU2001284924A AU8492401A AU2001284924A1 AU 2001284924 A1 AU2001284924 A1 AU 2001284924A1 AU 2001284924 A AU2001284924 A AU 2001284924A AU 8492401 A AU8492401 A AU 8492401A AU 2001284924 A1 AU2001284924 A1 AU 2001284924A1
- Authority
- AU
- Australia
- Prior art keywords
- random access
- dynamic random
- memory
- access memory
- cache memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
- G11C15/043—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using capacitive charge storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09642546 | 2000-08-17 | ||
US09/642,546 US6862654B1 (en) | 2000-08-17 | 2000-08-17 | Method and system for using dynamic random access memory as cache memory |
PCT/US2001/025494 WO2002015019A1 (en) | 2000-08-17 | 2001-08-14 | Method and system for using dynamic random access memory as cache memory |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001284924A1 true AU2001284924A1 (en) | 2002-02-25 |
Family
ID=24577039
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001284924A Abandoned AU2001284924A1 (en) | 2000-08-17 | 2001-08-14 | Method and system for using dynamic random access memory as cache memory |
Country Status (3)
Country | Link |
---|---|
US (5) | US6862654B1 (en) |
AU (1) | AU2001284924A1 (en) |
WO (1) | WO2002015019A1 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7123521B1 (en) | 2005-04-27 | 2006-10-17 | Micron Technology, Inc. | Random cache read |
US9455035B2 (en) * | 2006-04-26 | 2016-09-27 | Invention Science Fund I, Llc | Management of memory refresh power consumption |
US8161232B2 (en) * | 2006-04-26 | 2012-04-17 | The Invention Science Fund I, Llc | Periodically and empirically determined memory refresh intervals |
KR101975528B1 (en) | 2012-07-17 | 2019-05-07 | 삼성전자주식회사 | semiconductor memory cell array having fast array area and semiconductor memory including the same |
US20140146589A1 (en) * | 2012-11-29 | 2014-05-29 | Samsung Electronics Co., Ltd. | Semiconductor memory device with cache function in dram |
US20140264915A1 (en) * | 2013-03-15 | 2014-09-18 | Chao-Yuan Huang | Stacked Integrated Circuit System |
WO2015065426A1 (en) * | 2013-10-31 | 2015-05-07 | Hewlett-Packard Development Company, L.P. | Memory access for busy memory |
KR102373544B1 (en) | 2015-11-06 | 2022-03-11 | 삼성전자주식회사 | Memory Device and Memory System Performing Request-based Refresh and Operating Method of Memory Device |
Family Cites Families (56)
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US69325A (en) * | 1867-10-01 | photo-litho | ||
US6071A (en) * | 1849-01-30 | Improved lubricating compound | ||
JPS63247997A (en) | 1987-04-01 | 1988-10-14 | Mitsubishi Electric Corp | Semiconductor storage device |
CA2011518C (en) | 1989-04-25 | 1993-04-20 | Ronald N. Fortino | Distributed cache dram chip and control method |
JP2862948B2 (en) | 1990-04-13 | 1999-03-03 | 三菱電機株式会社 | Semiconductor storage device |
US5359722A (en) | 1990-07-23 | 1994-10-25 | International Business Machines Corporation | Method for shortening memory fetch time relative to memory store time and controlling recovery in a DRAM |
EP1293906A3 (en) | 1990-12-25 | 2004-05-19 | Mitsubishi Denki Kabushiki Kaisha | A semiconductor memory device with a large storage capacity memory and a fast speed memory |
US5414827A (en) | 1991-12-19 | 1995-05-09 | Opti, Inc. | Automatic cache flush |
EP0552667B1 (en) | 1992-01-22 | 1999-04-21 | Enhanced Memory Systems, Inc. | Enhanced dram with embedded registers |
US5471601A (en) | 1992-06-17 | 1995-11-28 | Intel Corporation | Memory device and method for avoiding live lock of a DRAM with cache |
JP3400824B2 (en) | 1992-11-06 | 2003-04-28 | 三菱電機株式会社 | Semiconductor storage device |
US5473770A (en) | 1993-03-02 | 1995-12-05 | Tandem Computers Incorporated | Fault-tolerant computer system with hidden local memory refresh |
JP3305056B2 (en) | 1993-08-31 | 2002-07-22 | 沖電気工業株式会社 | Dynamic RAM |
TW358907B (en) | 1994-11-22 | 1999-05-21 | Monolithic System Tech Inc | A computer system and a method of using a DRAM array as a next level cache memory |
US6128700A (en) | 1995-05-17 | 2000-10-03 | Monolithic System Technology, Inc. | System utilizing a DRAM array as a next level cache memory and method for operating same |
JPH0916470A (en) | 1995-07-03 | 1997-01-17 | Mitsubishi Electric Corp | Semiconductor storage device |
JPH0973776A (en) | 1995-09-07 | 1997-03-18 | Mitsubishi Electric Corp | Synchronous semiconductor memory |
US5835941A (en) | 1995-11-17 | 1998-11-10 | Micron Technology Inc. | Internally cached static random access memory architecture |
JP3352577B2 (en) | 1995-12-21 | 2002-12-03 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Storage device |
US6131140A (en) | 1995-12-22 | 2000-10-10 | Cypress Semiconductor Corp. | Integrated cache memory with system control logic and adaptation of RAM bus to a cache pinout |
US5677878A (en) | 1996-01-17 | 1997-10-14 | Micron Technology, Inc. | Method and apparatus for quickly restoring digit I/O lines |
US6061759A (en) | 1996-02-09 | 2000-05-09 | Apex Semiconductor, Inc. | Hidden precharge pseudo cache DRAM |
US5796671A (en) | 1996-03-01 | 1998-08-18 | Wahlstrom; Sven E. | Dynamic random access memory |
US5875451A (en) | 1996-03-14 | 1999-02-23 | Enhanced Memory Systems, Inc. | Computer hybrid memory including DRAM and EDRAM memory components, with secondary cache in EDRAM for DRAM |
US6404670B2 (en) | 1996-05-24 | 2002-06-11 | Uniram Technology, Inc. | Multiple ports memory-cell structure |
ES2150127T3 (en) * | 1996-05-28 | 2000-11-16 | Daimler Chrysler Ag | Procedure for joining components and constructive groups of railway vehicles by gluing |
US5813029A (en) | 1996-07-09 | 1998-09-22 | Micron Electronics, Inc. | Upgradeable cache circuit using high speed multiplexer |
TW349196B (en) | 1996-10-18 | 1999-01-01 | Ibm | Cached synchronous DRAM architecture having a mode register programmable cache policy |
US5787457A (en) | 1996-10-18 | 1998-07-28 | International Business Machines Corporation | Cached synchronous DRAM architecture allowing concurrent DRAM operations |
US5835401A (en) | 1996-12-05 | 1998-11-10 | Cypress Semiconductor Corporation | Dram with hidden refresh |
KR100242998B1 (en) | 1996-12-30 | 2000-02-01 | 김영환 | Structure of cell array and sense amplifier |
US6088760A (en) | 1997-03-07 | 2000-07-11 | Mitsubishi Semiconductor America, Inc. | Addressing system in a multi-port RAM having main and cache memories |
US6172927B1 (en) * | 1997-04-01 | 2001-01-09 | Ramtron International Corporation | First-in, first-out integrated circuit memory device incorporating a retransmit function |
US5991851A (en) | 1997-05-02 | 1999-11-23 | Enhanced Memory Systems, Inc. | Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control |
KR100554112B1 (en) | 1997-05-30 | 2006-02-20 | 미크론 테크놀로지,인코포레이티드 | 256 meg dynamic random access memory |
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US6023428A (en) | 1997-07-28 | 2000-02-08 | Texas Instruments Incorporated | Integrated circuit device having a memory array with segmented bit lines and method of operation |
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US6173356B1 (en) | 1998-02-20 | 2001-01-09 | Silicon Aquarius, Inc. | Multi-port DRAM with integrated SRAM and systems and methods using the same |
US6215497B1 (en) | 1998-08-12 | 2001-04-10 | Monolithic System Technology, Inc. | Method and apparatus for maximizing the random access bandwidth of a multi-bank DRAM in a computer graphics system |
US6415353B1 (en) | 1998-10-01 | 2002-07-02 | Monolithic System Technology, Inc. | Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same |
US5999474A (en) * | 1998-10-01 | 1999-12-07 | Monolithic System Tech Inc | Method and apparatus for complete hiding of the refresh of a semiconductor memory |
US6587918B1 (en) | 1998-11-19 | 2003-07-01 | Micron Technology, Inc. | Method for controlling refresh of a multibank memory device |
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US6226755B1 (en) | 1999-01-26 | 2001-05-01 | Compaq Computer Corp. | Apparatus and method for enhancing data transfer to or from a SDRAM system |
US6178133B1 (en) | 1999-03-01 | 2001-01-23 | Micron Technology, Inc. | Method and system for accessing rows in multiple memory banks within an integrated circuit |
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US6449690B1 (en) | 1999-06-25 | 2002-09-10 | Hewlett-Packard Company | Caching method using cache data stored in dynamic RAM embedded in logic chip and cache tag stored in static RAM external to logic chip |
US6445636B1 (en) | 2000-08-17 | 2002-09-03 | Micron Technology, Inc. | Method and system for hiding refreshes in a dynamic random access memory |
AU2001289169A1 (en) | 2000-08-30 | 2002-03-13 | Micron Technology, Inc. | Semiconductor memory having dual port cell supporting hidden refresh |
US6697909B1 (en) | 2000-09-12 | 2004-02-24 | International Business Machines Corporation | Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory |
US6779076B1 (en) * | 2000-10-05 | 2004-08-17 | Micron Technology, Inc. | Method and system for using dynamic random access memory as cache memory |
US6629188B1 (en) | 2000-11-13 | 2003-09-30 | Nvidia Corporation | Circuit and method for prefetching data for a texture cache |
-
2000
- 2000-08-17 US US09/642,546 patent/US6862654B1/en not_active Expired - Fee Related
-
2001
- 2001-08-14 WO PCT/US2001/025494 patent/WO2002015019A1/en active Application Filing
- 2001-08-14 AU AU2001284924A patent/AU2001284924A1/en not_active Abandoned
-
2004
- 2004-03-30 US US10/815,877 patent/US6948027B2/en not_active Expired - Fee Related
-
2005
- 2005-09-19 US US11/230,836 patent/US7155561B2/en not_active Expired - Fee Related
-
2006
- 2006-11-08 US US11/595,370 patent/US7350018B2/en not_active Expired - Fee Related
-
2008
- 2008-02-12 US US12/069,812 patent/US7917692B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6862654B1 (en) | 2005-03-01 |
US7917692B2 (en) | 2011-03-29 |
US20080177943A1 (en) | 2008-07-24 |
US20040186957A1 (en) | 2004-09-23 |
US7350018B2 (en) | 2008-03-25 |
US7155561B2 (en) | 2006-12-26 |
US6948027B2 (en) | 2005-09-20 |
WO2002015019A1 (en) | 2002-02-21 |
US20070055818A1 (en) | 2007-03-08 |
US20060015679A1 (en) | 2006-01-19 |
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