AU2001253074A1 - Multi-tiered memory bank having different data buffer sizes with a programmable bank select - Google Patents

Multi-tiered memory bank having different data buffer sizes with a programmable bank select

Info

Publication number
AU2001253074A1
AU2001253074A1 AU2001253074A AU5307401A AU2001253074A1 AU 2001253074 A1 AU2001253074 A1 AU 2001253074A1 AU 2001253074 A AU2001253074 A AU 2001253074A AU 5307401 A AU5307401 A AU 5307401A AU 2001253074 A1 AU2001253074 A1 AU 2001253074A1
Authority
AU
Australia
Prior art keywords
data buffer
different data
bank
programmable
buffer sizes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001253074A
Other languages
English (en)
Inventor
Michael Allen
Jose Fridman
Marc Hoffman
Hebbalalu S. Ramagopal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001253074A1 publication Critical patent/AU2001253074A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G06F2212/2515—Local memory within processor subsystem being configurable for different purposes, e.g. as cache or non-cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU2001253074A 2000-03-31 2001-03-30 Multi-tiered memory bank having different data buffer sizes with a programmable bank select Abandoned AU2001253074A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09541114 2000-03-31
US09/541,114 US6606684B1 (en) 2000-03-31 2000-03-31 Multi-tiered memory bank having different data buffer sizes with a programmable bank select
PCT/US2001/010573 WO2001075607A2 (en) 2000-03-31 2001-03-30 Multi-tiered memory bank having different data buffer sizes with a programmable bank select

Publications (1)

Publication Number Publication Date
AU2001253074A1 true AU2001253074A1 (en) 2001-10-15

Family

ID=24158229

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001253074A Abandoned AU2001253074A1 (en) 2000-03-31 2001-03-30 Multi-tiered memory bank having different data buffer sizes with a programmable bank select

Country Status (6)

Country Link
US (2) US6606684B1 (zh)
EP (1) EP1269323A2 (zh)
CN (1) CN1201233C (zh)
AU (1) AU2001253074A1 (zh)
TW (1) TW535054B (zh)
WO (1) WO2001075607A2 (zh)

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US7333530B1 (en) * 2001-08-06 2008-02-19 Analog Devices, Inc. Despread signal recovery in digital signal processors
US6981122B2 (en) * 2002-09-26 2005-12-27 Analog Devices, Inc. Method and system for providing a contiguous memory address space
US7775966B2 (en) 2005-02-24 2010-08-17 Ethicon Endo-Surgery, Inc. Non-invasive pressure measurement in a fluid adjustable restrictive device
US7775215B2 (en) 2005-02-24 2010-08-17 Ethicon Endo-Surgery, Inc. System and method for determining implanted device positioning and obtaining pressure data
US7658196B2 (en) 2005-02-24 2010-02-09 Ethicon Endo-Surgery, Inc. System and method for determining implanted device orientation
US7699770B2 (en) 2005-02-24 2010-04-20 Ethicon Endo-Surgery, Inc. Device for non-invasive measurement of fluid pressure in an adjustable restriction device
US8112755B2 (en) * 2006-06-30 2012-02-07 Microsoft Corporation Reducing latencies in computing systems using probabilistic and/or decision-theoretic reasoning under scarce memory resources
US7640397B2 (en) * 2006-10-11 2009-12-29 Arm Limited Adaptive comparison control in a memory
US7991960B2 (en) * 2006-10-11 2011-08-02 Arm Limited Adaptive comparison control in a data store
US8635390B2 (en) * 2010-09-07 2014-01-21 International Business Machines Corporation System and method for a hierarchical buffer system for a shared data bus
KR101788245B1 (ko) * 2011-02-25 2017-11-16 삼성전자주식회사 다중 포트 캐시 메모리 장치 및 그 구동 방법
WO2013091192A1 (zh) * 2011-12-21 2013-06-27 华为技术有限公司 提供多设备镜像和条带功能的磁盘缓存方法、设备和系统
US9298389B2 (en) 2013-10-28 2016-03-29 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Operating a memory management controller
KR102533236B1 (ko) 2016-06-20 2023-05-17 삼성전자주식회사 개선된 레이턴시를 갖는 메모리 장치 및 그것의 동작 방법
US20220180162A1 (en) * 2020-12-08 2022-06-09 Electronics And Telecommunications Research Institute Ai accelerator, cache memory and method of operating cache memory using the same

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JPH09503609A (ja) * 1994-02-25 1997-04-08 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン ビット・マッピングの装置および方法
US5611075A (en) 1994-10-04 1997-03-11 Analog Devices, Inc. Bus architecture for digital signal processor allowing time multiplexed access to memory banks
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US6446181B1 (en) * 2000-03-31 2002-09-03 Intel Corporation System having a configurable cache/SRAM memory

Also Published As

Publication number Publication date
TW535054B (en) 2003-06-01
CN1426558A (zh) 2003-06-25
WO2001075607A2 (en) 2001-10-11
WO2001075607A3 (en) 2002-05-23
US6898690B2 (en) 2005-05-24
US20040034739A1 (en) 2004-02-19
US6606684B1 (en) 2003-08-12
CN1201233C (zh) 2005-05-11
EP1269323A2 (en) 2003-01-02

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