AU2002217924A1 - Scheduler for a data memory access having multiple channels - Google Patents

Scheduler for a data memory access having multiple channels

Info

Publication number
AU2002217924A1
AU2002217924A1 AU2002217924A AU1792402A AU2002217924A1 AU 2002217924 A1 AU2002217924 A1 AU 2002217924A1 AU 2002217924 A AU2002217924 A AU 2002217924A AU 1792402 A AU1792402 A AU 1792402A AU 2002217924 A1 AU2002217924 A1 AU 2002217924A1
Authority
AU
Australia
Prior art keywords
scheduler
memory access
data memory
multiple channels
channels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002217924A
Inventor
Ravikrishna Cherukuri
Ranjit J. Rozario
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Redback Networks Inc
Original Assignee
Redback Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Redback Networks Inc filed Critical Redback Networks Inc
Publication of AU2002217924A1 publication Critical patent/AU2002217924A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0674—Disk device
AU2002217924A 2000-12-18 2001-11-29 Scheduler for a data memory access having multiple channels Abandoned AU2002217924A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/740,669 2000-12-18
US09/740,669 US7254651B2 (en) 2000-12-18 2000-12-18 Scheduler for a direct memory access device having multiple channels
PCT/US2001/044580 WO2002050626A2 (en) 2000-12-18 2001-11-29 Scheduler for a data memory access having multiple channels

Publications (1)

Publication Number Publication Date
AU2002217924A1 true AU2002217924A1 (en) 2002-07-01

Family

ID=24977527

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002217924A Abandoned AU2002217924A1 (en) 2000-12-18 2001-11-29 Scheduler for a data memory access having multiple channels

Country Status (5)

Country Link
US (1) US7254651B2 (en)
EP (1) EP1344138A4 (en)
JP (1) JP2004527024A (en)
AU (1) AU2002217924A1 (en)
WO (1) WO2002050626A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7869453B2 (en) * 2004-12-17 2011-01-11 Lantiq Deutschland Gmbh Apparatus and method for data transfer
US7493426B2 (en) * 2005-01-31 2009-02-17 International Business Machines Corporation Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction control
US7136954B2 (en) * 2005-01-31 2006-11-14 International Business Machines Corporation Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism
US20060174050A1 (en) * 2005-01-31 2006-08-03 International Business Machines Corporation Internal data bus interconnection mechanism utilizing shared buffers supporting communication among multiple functional components of an integrated circuit chip
US7620746B2 (en) * 2005-09-29 2009-11-17 Apple Inc. Functional DMA performing operation on DMA data and writing result of operation
US7496695B2 (en) * 2005-09-29 2009-02-24 P.A. Semi, Inc. Unified DMA
US20080285551A1 (en) * 2007-05-18 2008-11-20 Shamsundar Ashok Method, Apparatus, and Computer Program Product for Implementing Bandwidth Capping at Logical Port Level for Shared Ethernet Port
JP2010108300A (en) * 2008-10-30 2010-05-13 Hitachi Ltd Information processing system, and method of allocating i/o to path in information processing system
US10996980B2 (en) * 2018-04-23 2021-05-04 Avago Technologies International Sales Pte. Limited Multi-threaded command processing system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04367058A (en) 1991-06-14 1992-12-18 Matsushita Electric Ind Co Ltd Information device
TW207013B (en) * 1993-02-19 1993-06-01 Nat Science Committee Architecture of optimal high-speed sorter
US5828856A (en) 1994-01-28 1998-10-27 Apple Computer, Inc. Dual bus concurrent multi-channel direct memory access controller and method
JPH1040211A (en) 1996-04-30 1998-02-13 Texas Instr Inc <Ti> Method for directly assigning memory access priority in packeted data communication interface equipment and dma channel circuit
US5938743A (en) 1997-03-17 1999-08-17 Xerox Corporation Method of using the UNIX physio to allow data to be transferred on a plurality of channels concurrently
US6052375A (en) 1997-11-26 2000-04-18 International Business Machines Corporation High speed internetworking traffic scaler and shaper

Also Published As

Publication number Publication date
US7254651B2 (en) 2007-08-07
US20020078267A1 (en) 2002-06-20
WO2002050626A3 (en) 2002-08-22
JP2004527024A (en) 2004-09-02
EP1344138A2 (en) 2003-09-17
WO2002050626A2 (en) 2002-06-27
EP1344138A4 (en) 2007-12-05

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