AU2001270884A1 - Memory resource arbitrator for multiple gate arrays - Google Patents

Memory resource arbitrator for multiple gate arrays

Info

Publication number
AU2001270884A1
AU2001270884A1 AU2001270884A AU7088401A AU2001270884A1 AU 2001270884 A1 AU2001270884 A1 AU 2001270884A1 AU 2001270884 A AU2001270884 A AU 2001270884A AU 7088401 A AU7088401 A AU 7088401A AU 2001270884 A1 AU2001270884 A1 AU 2001270884A1
Authority
AU
Australia
Prior art keywords
gate arrays
memory resource
multiple gate
resource arbitrator
arbitrator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001270884A
Inventor
Alex Wilson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Celoxica Ltd
Original Assignee
Celoxica Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Celoxica Ltd filed Critical Celoxica Ltd
Publication of AU2001270884A1 publication Critical patent/AU2001270884A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
AU2001270884A 2000-07-20 2001-07-19 Memory resource arbitrator for multiple gate arrays Abandoned AU2001270884A1 (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US21980800P 2000-07-20 2000-07-20
US60219808 2000-07-20
US68748100A 2000-10-12 2000-10-12
US68701200A 2000-10-12 2000-10-12
US09687012 2000-10-12
US09687481 2000-10-12
PCT/GB2001/003258 WO2002008913A2 (en) 2000-07-20 2001-07-19 Memory resource arbitrator for multiple gate arrays

Publications (1)

Publication Number Publication Date
AU2001270884A1 true AU2001270884A1 (en) 2002-02-05

Family

ID=27396704

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001270884A Abandoned AU2001270884A1 (en) 2000-07-20 2001-07-19 Memory resource arbitrator for multiple gate arrays

Country Status (3)

Country Link
US (1) US20020010825A1 (en)
AU (1) AU2001270884A1 (en)
WO (1) WO2002008913A2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7139743B2 (en) 2000-04-07 2006-11-21 Washington University Associative database scanning and information retrieval using FPGA devices
US7711844B2 (en) * 2002-08-15 2010-05-04 Washington University Of St. Louis TCP-splitter: reliable packet monitoring methods and apparatus for high speed networks
US10572824B2 (en) 2003-05-23 2020-02-25 Ip Reservoir, Llc System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines
EP1627331B1 (en) 2003-05-23 2017-09-20 IP Reservoir, LLC Intelligent data storage and processing using fpga devices
EP1859378A2 (en) * 2005-03-03 2007-11-28 Washington University Method and apparatus for performing biosequence similarity searching
US7840482B2 (en) * 2006-06-19 2010-11-23 Exegy Incorporated Method and system for high speed options pricing
US7921046B2 (en) 2006-06-19 2011-04-05 Exegy Incorporated High speed processing of financial information using FPGA devices
US8326819B2 (en) * 2006-11-13 2012-12-04 Exegy Incorporated Method and system for high performance data metatagging and data indexing using coprocessors
US7730278B2 (en) * 2007-07-12 2010-06-01 Oracle America, Inc. Chunk-specific executable code for chunked java object heaps
US10229453B2 (en) 2008-01-11 2019-03-12 Ip Reservoir, Llc Method and system for low latency basket calculation
EP2370946A4 (en) 2008-12-15 2012-05-30 Exegy Inc Method and apparatus for high-speed processing of financial market depth data
US10037568B2 (en) 2010-12-09 2018-07-31 Ip Reservoir, Llc Method and apparatus for managing orders in financial markets
US9990393B2 (en) 2012-03-27 2018-06-05 Ip Reservoir, Llc Intelligent feed switch
US10650452B2 (en) 2012-03-27 2020-05-12 Ip Reservoir, Llc Offload processing of data packets
US11436672B2 (en) 2012-03-27 2022-09-06 Exegy Incorporated Intelligent switch for processing financial market data
US10121196B2 (en) 2012-03-27 2018-11-06 Ip Reservoir, Llc Offload processing of data packets containing financial market data
EP3560135A4 (en) 2016-12-22 2020-08-05 IP Reservoir, LLC Pipelines for hardware-accelerated machine learning

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05298115A (en) * 1992-04-23 1993-11-12 Toshiba Corp Device and method for processing data
JPH08194656A (en) * 1995-01-13 1996-07-30 Meidensha Corp Managing method for transmission/reception buffer
US5737766A (en) * 1996-02-14 1998-04-07 Hewlett Packard Company Programmable gate array configuration memory which allows sharing with user memory

Also Published As

Publication number Publication date
WO2002008913A2 (en) 2002-01-31
US20020010825A1 (en) 2002-01-24
WO2002008913A3 (en) 2002-05-02

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