JPH05298115A - Device and method for processing data - Google Patents

Abstract

PURPOSE:To improve versatility and to enable programming at the user level by performing processing corresponding to the program length of a sub routine in a source program while using plural programmable hardware circuits. CONSTITUTION:The sub routine longer than the specified length is compiled by the plural programmable hardware circuits such as field programmable gate arrays(FPGA) 151-15n corresponding to the program length of the sub routine in the source program while using those hardware circuits. On the other hand, the sub routine shorter than the specified length is compiled by an execution file as it is and processed by softwares. Prepared mapping and execution files are preserved in a RAM 14 as a shared memory. Thus, when the stored execution file is read and started, a CPU 11 loads the mapping files of (n) pieces of FPGA from the RAM 14 and obtains the sub routine as a wave motion circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus and method for compiling a source program created in a high-level language into an execution file and executing data processing.

[0002]

2. Description of the Related Art Conventionally, in the case of performing complicated and time-consuming data processing, either a program is used to handle it by software, or dedicated hardware such as a gate array is developed to handle it. It was realized by the method.

In general, the former software method can be easily implemented by the user, but it is difficult to increase the processing speed, the processing time cannot be shortened, and an enormous memory capacity is required, which is efficient. In many cases, the latter hardware method described above is used for this reason.

However, even with this hardware method, the processing speed can be improved and the memory capacity can be limited, but on the other hand, it takes a long time and cost for development, and the versatility is poor. It had the drawback of having to redevelop it.

[0005]

As described above, the software method is difficult to speed up and requires a huge memory capacity, and the hardware method requires development in a long period of time and cost, and is not versatile. Because of the drawbacks
The user selects and implements the lesser degree of failure depending on the occasion.

The present invention has been made in view of the above circumstances, and an object thereof is to have high versatility, enable programming at a user level, high processing speed, and memory capacity. It is to provide a data processing device and method that can be limited.

[0007]

SUMMARY OF THE INVENTION That is, the present invention provides a plurality of programmable hardware circuits such as a field programmable gate array (FPGA) (user programmable gate array). ) Is used to compile a subroutine with a specific length or longer corresponding to the program length of the subroutine in the source program into the programmable hardware circuit, while a subroutine shorter than the specific length is directly compiled into an executable file and processed by software. Therefore, the versatility is high, programming at the user level is possible, and at the same time, the memory capacity is not limited, and high-speed processing is possible and efficient data processing can be performed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit configuration thereof. 11 is a CPU for integrally controlling the entire apparatus, 12 is a peripheral L for controlling an external interface, a system bus SB and the like.
SI, 13 is a ROM for storing system programs and BIOS, 14 is a RAM used as a shared memory, 151
, 152, ..., 15n are FPGAs as programmable hardware circuits.

Each of the FPGAs 151, 152, ..., 15n is, for example, 20 × 10 ^3. It is composed of an LSI chip in which individual gate elements are arranged in an array, and a desired hardware circuit is realized by compiling a subroutine. Here, n pieces are provided.

With the above-mentioned structure, the operation is as shown in FIG. That is, this figure shows the processing contents from the creation of the source program to the storage of the execution file in the RAM 14 which is a shared memory, and the overall operation control is performed by the CPU 11.

At the beginning of the process, first, as shown in step S1, the user creates a source program in a high-level language, including a subroutine if necessary. When the creation of the program is completed, the CPU 11 subsequently determines in step S2 whether or not there is a subroutine in the source program.

If there is a subroutine, it is further determined in step S5 whether or not the program length of the subroutine is long, for example, based on a specific number of program steps. When there is a subroutine having a long program length and requiring a long time processing, a mapping file is created in the FPGA 151, 152, ..., 15n by compiling the subroutine in step S6 by the compiler for FPGA. ..

If it is determined in step S2 that there is no subroutine but only the main routine, or if there is a subroutine, it is determined in step S5 that it is a short subroutine that does not require long-time processing. If determined, the main routine and the subroutine are compiled by the high-level language compiler stored in the ROM 13 in advance to create an execution file.

Then, in step S4, the mapping file created in step S6 and step S3
The executable file created in step S6 is saved in the RAM 14 which is a shared memory.

When the execution file stored in the RAM 14 is read and activated in this way, the CPU 11 reads n from the RAM 14.
, 15n FPGA15, 152, ... 15n mapping file is loaded and a predetermined number of subroutines FPGA151
, 152, ..., 15n are realized as a wave circuit.

Then, the execution file of the source program is moved to the RAM 14 and executed by the CPU 11. At this time, when calling a subroutine that requires a long processing time, the CPU 151 pre-configures the hardware in the FPGA 151.
, 152, ..., 15n to execute the data processing, the subroutine can be processed at high speed. The CPU 11 continues the execution file again after receiving the result, and executes the above processing until the main routine of the source program is completed.

In the above embodiment, whether or not a subroutine requiring a long-time process is realized by hardware in FPGA 151, 152, ..., 15n is automatically judged and executed. It is also possible for the user to judge whether or not to implement hardware for each individual subroutine and to specify and compile it. Also, FPG
.., 15n may be automatically loaded when a subroutine is called in the execution file of the source program, instead of finishing all the loading of the subroutines into A151, 152, ..., 15n.

Further, when the number of FPGAs 151, 152, ..., 15n used as programmable hardware circuits is limited, n FPGAs 151, 152 ,.
When m subroutines (n> m) in 15n are compiled, the remaining subroutines may be set to be compiled into an executable file together with the main routine regardless of the length required for the processing. ..

[0020]

As described above, according to the present invention, a plurality of programmable hardware circuits such as FPGAs are used.
, A subroutine having a specific length or more corresponding to the program length of the subroutine in the source program is compiled into the programmable hardware circuit,
Subroutines shorter than a specified length are compiled into an executable file and processed by software, so they have high versatility and can be programmed at the user level, and at the same time do not limit the memory capacity and enable high-speed processing. Data processing can be performed efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating the operation of the present invention.

[Explanation of symbols]

11 ... CPU, 12 ... Peripheral LSI, 13 ... ROM, 14
... RAM, 151, 152, 15n ... FPGA.

Claims (3)

[Claims] 1. A plurality of programmable hardware circuits, a first compiling means for creating a mapping file of these programmable hardware circuits, and a source program created by a user in a high-level language is compiled into an execution file. The second compiling means and a subroutine having a specific length or more corresponding to the program length of the subroutine in the source program are compiled into the programmable hardware circuit by the first compiling means, and a subroutine shorter than the specific length is A data processing apparatus comprising: a control unit that causes the second compiling unit to compile an execution file. 2. The data processing apparatus according to claim 1, wherein the programmable hardware circuit comprises a field programmable gate array. 3. Data corresponding to a program length of a subroutine in a source program, wherein a subroutine having a specific length or more is compiled into a programmable hardware circuit, and a subroutine shorter than the specific length is compiled into an execution file. Processing method.