JP4578884B2 - Program converter - Google Patents

Description

  The present invention relates to a program conversion apparatus that converts a processing program for executing a series of preset processes into a new processing program for executing the same processing content.

  In general, control devices for machines and devices such as NC machine tools are provided with a CPU, ROM and RAM, and the CPU reads a system control program stored in the ROM or RAM in advance from the ROM or RAM and executes it. By doing so, it is configured to control the machine or device.

  However, since the execution speed of the CPU greatly depends on the performance of the CPU, when a low-performance CPU is used, it cannot be processed at a high speed such as a response delay, and the system control is not accurate. There is a problem that it cannot be performed well, and when a high-performance CPU is used, there is a problem that the manufacturing cost increases.

  Therefore, in recent years, a part of the system control program is written in a programmable logic circuit such as an FPGA (Field Programmable Gate Array), and a part of the processing executed by the CPU is executed by the logic circuit. It has been proposed. In this way, since the processing speed of the logic circuit is higher than that of the CPU, the entire system control program can be processed at high speed, and system control can be performed with high accuracy.

  The writing of the program to the logic circuit is conventionally performed as follows. First, the operator repeats a predetermined number of times or more in a system control program created in a software program language such as C language. The process to be executed is searched, and the program of the part that is the repeated process is extracted.

  Thereafter, the extracted program is converted into a subroutine, and the original system control program is deleted from the repeated processing portion of the system control program, and the repeated processing is executed by the subroutine. Convert to Next, the program language of the program converted into a subroutine is converted into a hardware description language for operating the logic circuit using an appropriate conversion device or the like, and the converted program is written in the logic circuit, while the program of the main routine is written. Write to ROM.

  As a result, in the system control program, processing of the main routine portion is executed by the CPU, and processing of the subroutine portion (repetitive processing portion) is executed by the logic circuit. In addition, since the processing of the repetitive portion is made into a subroutine and executed by a logic circuit, it is possible to reduce the amount of program data in the main routine and to improve the processing speed of the system control program more effectively. You can also

Masahiro Fujita, “Design Wave Magazine”, February 2003, QC Publishing, February 1, 2003, p. 20-p. 25

  However, as described above, the operator extracts a program for processing to be executed repeatedly over a predetermined number of times from the entire system control program and converts it into a subroutine, or changes the program language of the extracted program to a hardware description language. If the original system control program was converted so that it could be converted or executed in a subroutine, it would take a long time to perform these operations, and there would be problems such as inefficiency and program conversion. If a mistake was made, there was a problem that an abnormality occurred in the system control.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a program conversion apparatus capable of efficiently and accurately converting a program.

To achieve the above object, the present invention provides:
A program for performing a series of processes including a plurality of different execution instructions, each of which is sequentially executed according to a preset order, and a part of each of the execution instructions is executed a plurality of times. Based on the processing program configured as described above, a first program as a main routine and a second program as a subroutine are generated, and the processing program is converted into a new process including the first program and the second program. A device for converting into a program,
An original program storage unit that stores the processing program before conversion, and stores each execution instruction in association with an address in the storage unit;
An execution processing unit that sequentially reads out the execution instruction from the address in the original program storage unit in which the execution instruction is stored according to the execution order, and executes the processing program;
An address storage unit for storing the address;
A monitoring processing unit that monitors processing in the execution processing unit and stores the addresses of the execution instructions sequentially executed by the execution processing unit in the address storage unit in the order in which the execution instructions are executed;
Based on the addresses stored in the address storage unit, the arrangement is confirmed, and it is confirmed whether there are more than a preset number of portions where the addresses are arranged in a certain number or more in the same order, When it is confirmed that there are more than the set number, an extraction processing unit that extracts each address of the corresponding part as it is,
Based on the address extracted by the extraction processing unit and the processing program stored in the original program storage unit, the execution instructions corresponding to the extraction address are sequentially executed in the order in which the extraction addresses are arranged. The second program and the series of processes are executed, and the processes sequentially executed by the execution instructions corresponding to the extraction addresses in the series of processes are executed by the second program. A conversion processing unit that generates the first program configured as described above and converts the processing program before conversion into a new processing program including the generated first program and second program;
A program conversion apparatus comprising: a generated program storage unit that stores a first program and a second program generated by the conversion processing unit.

  According to this invention, first, a processing program for performing a predetermined series of processing to be converted is stored in the original program storage unit. The processing program includes a plurality of different execution instructions, and each execution instruction is sequentially executed according to a predetermined order, and a part of each execution instruction is executed a plurality of times. Execution instructions are stored in association with addresses in the storage unit. An example of such a processing program is a system control program for controlling machines and devices such as NC machine tools.

  Then, when the execution program is sequentially read out from the corresponding address in the original program storage unit according to the execution order by the execution processing unit and the processing program is executed, the monitoring processing unit monitors the processing in the execution processing unit Thus, the addresses of the execution instructions sequentially executed by the execution processing unit are stored in the address storage unit in the execution order.

  Thereafter, the arrangement is confirmed by the extraction processing unit based on the addresses stored in the address storage unit, and it is confirmed whether or not there are a predetermined number or more of parts where the addresses are arranged in a certain number in the same order. If it is confirmed that there are a predetermined number or more, each address of the corresponding part is extracted as it is. On the other hand, if it is not confirmed that there are a predetermined number or more, the above series of processing ends. The fixed number and the predetermined number are appropriately set according to the processing content of the processing program, the amount of program data, and the like. If the number of addresses to be extracted increases, the amount of data of the second program generated by the conversion processing unit increases and may exceed the storage capacity of the logic circuit described later. The upper limit value is set for the number of addresses, and it is configured to check whether there are more than a predetermined number of addresses arranged in the same order and a certain number (lower limit value) or more and less than the upper limit value. It is preferable.

  When the address is extracted by the extraction processing unit, each execution instruction corresponding to the extraction address is converted by the conversion processing unit based on the address extracted by the extraction processing unit and the processing program stored in the original program storage unit. Are executed in the order in which the extracted addresses are arranged, and the second program, which is a subroutine, and the series of processes are executed, and each execution instruction corresponding to the extracted address is included in the series of processes. A first program that is a main routine configured to be executed by the second program is generated for the processing that is sequentially executed, and the pre-conversion processing program is generated by the generated first program and second program. Is converted into a new processing program.

  The first program and the second program generated by the conversion processing unit are stored in the generated program storage unit by the conversion processing unit.

  The conversion processing unit is preferably configured to generate the second program as a program for operating a programmable logic circuit such as an FPGA, for example. Write processing unit for writing the first program and the second program stored in the generated program storage unit into the storage device such as ROM and RAM for the first program, and the logic circuit for the second program It is preferable to further comprise.

The present invention also provides:
A processing program comprising a plurality of subroutines configured to execute different processing contents and a main routine configured to execute a series of preset processes by executing the subroutines. An apparatus for converting into a new processing program including a logic circuit program for operating a possible logic circuit,
An original program storage unit that stores the processing program before conversion, and stores each subroutine in association with an address in the storage unit;
An execution processing unit that executes a main routine stored in the original program storage unit and reads and executes the subroutine from an address in the original program storage unit in which the subroutine is stored;
An address storage unit for storing the address;
A monitoring processing unit that monitors processing in the execution processing unit and stores the address of a subroutine executed by the execution processing unit in the address storage unit each time the subroutine is executed;
Based on the address stored in the address storage unit, the number for each address is counted to check whether there is an address exceeding the preset number, and the address exceeding the set number If it is confirmed that there is, the extraction processing unit that extracts the address,
Based on the address extracted by the extraction processing unit and the processing program stored in the original program storage unit, a subroutine corresponding to the extraction address is converted into the logic circuit program, and The main routine is converted into a new main routine configured to execute the processing executed by the subroutine corresponding to the extracted address by the converted logic circuit program, and the processing program before the conversion is converted. A conversion processing unit that converts the converted logic circuit program and main routine into a new processing program including the unconverted subroutines;
A program conversion apparatus comprising: a logic circuit program converted by the conversion processing unit and a conversion program storage unit for storing at least a main routine.

  According to this invention, similarly to the above, first, the processing program to be converted is stored in the original program storage unit. This processing program is composed of a plurality of subroutines for executing different processing contents and a main routine for executing each subroutine and executing a predetermined series of processing. Stored in association with each other.

  When the main routine stored in the original program storage unit is executed by the execution processing unit and the subroutine is read from the corresponding address in the original program storage unit and executed, the processing in the execution processing unit is performed. The monitoring processing unit for monitoring the address of the subroutine executed by the execution processing unit is stored in the address storage unit every time the subroutine is executed.

  Thereafter, the number of each address is counted by the extraction processing unit based on the address stored in the address storage unit, and it is confirmed whether there is an address exceeding the predetermined number. If it is confirmed that there is an exceeding address, the address is extracted. On the other hand, if it is not confirmed that there are more addresses than the predetermined number, the above series of processing ends. The predetermined number is appropriately set according to the processing contents of the processing program.

  When the address is extracted by the extraction processing unit, the conversion processing unit, based on the address extracted by the extraction processing unit and the processing program stored in the original program storage unit, a subroutine corresponding to the extraction address, For example, a process for converting to a logic circuit program for operating a programmable logic circuit such as an FPGA, and a process executed by a subroutine corresponding to the extracted address in the series of processes is performed for the logic circuit. The main routine is converted into a new main routine configured to be executed by a program, and the pre-conversion processing program is the logic circuit program and main routine after conversion, and the unconverted subroutines. Is converted into a new processing program.

  Then, at least the logic circuit program and the main routine converted by the conversion processing unit are stored in the conversion program storage unit by the conversion processing unit.

  The program conversion apparatus stores the logic circuit program and the main routine stored in the conversion program storage unit, the logic circuit program in the logic circuit, and the main routine, for example, ROM, RAM, etc. It is preferable to further include a writing processing unit for writing to the storage device.

  As described above, according to the program conversion device of the present invention, when there are a predetermined number or more of portions where the addresses of the execution instructions are arranged in a certain number or more in the same order, the execution is performed by each execution instruction of the portion The second process is determined to be a repetitive process, a second program in which the repetitive process is converted into a subroutine is generated, and the repetitive process is a main routine configured to cause the second program to execute the process. By generating one program, the processing program to be converted is automatically converted into a new processing program consisting of a first program (main routine) and a second program (subroutine), so that the conversion process is efficient and accurate. It can be performed.

  Further, when there is an address of a subroutine that exceeds a predetermined set number, the process executed by the subroutine is determined to be a repetition process, and the program for the repetition process is converted into a logic circuit program. As for the processing, by converting the main routine before the conversion into a new main routine configured to execute the processing by the logic circuit program, the conversion target processing program is converted into the converted logic circuit program and Since the program is automatically converted into a new processing program consisting of the main routine and unconverted subroutines, the conversion process can be performed efficiently and accurately even in this case.

  Further, if the conversion processing unit is configured to generate the second program as a program for operating the programmable logic circuit, the program language of the generated second program is changed to a program language corresponding to the logic circuit. Therefore, it is not necessary to convert the data into a new one, so that it is efficient and an accurate program for the logic circuit can be obtained.

  If the program conversion device is further provided with a write processing unit, the first program and the second program stored in the generated program storage unit, the logic circuit program and the main routine stored in the conversion program storage unit Can be automatically written to a storage device or a logic circuit as appropriate, so that the writing process can be performed efficiently.

  Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of a program conversion apparatus according to an embodiment of the present invention.

  As shown in FIG. 1, the program conversion apparatus 1 of this example is composed of a CPU, a ROM, a RAM, a hard disk, and the like, and includes an original program storage unit 11, an execution processing unit 12, a monitoring processing unit 13, an address storage unit 14, and an extraction. A processing unit 15, an extracted address storage unit 16, a conversion processing unit 17, a generated program storage unit 18, and a writing processing unit 19 are provided.

  The original program storage unit 11 stores a processing program for performing a predetermined series of processes to be converted. This processing program is, for example, a system control program for an NC machine tool that is created in a software program language such as C language and then converted into a machine language, and includes a plurality of different execution instructions. While being executed sequentially according to a predetermined order as shown in FIG. 2, a part of each execution instruction is repeatedly executed a plurality of times. As shown in FIG. 3, the execution instructions and data necessary for the execution are stored in association with addresses in the storage unit.

  The execution processing unit 12 sequentially reads the execution instructions from the address in the original program storage unit 11 where the execution instructions are stored according to the execution order, and executes the processing program.

  The monitoring processing unit 13 monitors the processing in the execution processing unit 12 and stores the addresses of the execution instructions sequentially executed by the execution processing unit 12 in the address storage unit 14 in the order in which the execution instructions are executed. Process to store. The data structure of the address stored in the address storage unit 14 is a data table as shown in FIG.

  The extraction processing unit 15 confirms the arrangement based on the addresses stored in the address storage unit 14, and the addresses are arranged in the same order and in a certain range (for example, 5 or more and 100 or less). Check if there are more than the preset number (for example, three or more), and if there are more than the set number, extract each address of the corresponding part as it is Then, the extracted address is stored in the extracted address storage unit 16. The predetermined range and the preset number are appropriately set according to the processing content of the processing program, the amount of program data, and the like. In addition, the upper limit is set for the number of addresses arranged (extracted) in the same order because the conversion processor 17 generates a second value as described later when the number of addresses to be extracted increases. This is because the data amount of the program becomes large and may exceed the storage capacity of the logic circuit 22.

  For example, in the address example shown in FIG. 4, as addresses arranged in the same order, address 3 and address 4, address 6, address 7, address 8, address 9, address 10, and address 11 are given. 2 for address 4 and 3 for address 6, address 7, address 8, address 9, address 10 and address 11. Therefore, address 6, address 7, address 8, address 9, address 10, and address 11 are extracted and stored in the extracted address storage unit 16 as addresses that satisfy the predetermined range and a predetermined number of conditions.

  Based on the extracted address stored in the extracted address storage unit 16 and the processing program stored in the original program storage unit 11, the conversion processing unit 17 includes a first program serving as a main routine and a second program serving as a subroutine. Is generated, and the processing program is converted into a new processing program including the generated first program and second program.

  Specifically, the conversion processing unit 17 first determines all source codes (C) of the processing program based on the processing program stored in the original program storage unit 11 and the extraction address stored in the extraction address storage unit 16. Language program) and source code for sequentially executing the execution instructions corresponding to the extracted addresses in the order in which the extracted addresses are arranged.

  Next, the recognized source code of each execution instruction corresponding to the extracted address is converted into a hardware description language for operating a programmable logic circuit 22 such as an FPGA to generate the second program. The source code of each execution instruction corresponding to the extracted address is deleted from all the recognized source codes, and the series of processes is executed, and each execution instruction corresponding to the extraction address is included in the series of processes. For the processing to be executed sequentially, the first program configured to be executed by the second program is generated.

  Thereby, for example, in the processing program executed in the execution order shown in FIG. 2, the execution instructions are sequentially executed by the first program as a main routine and the second program as a subroutine as shown in FIG. It is converted into such a new processing program. Then, the conversion processing unit 17 stores the generated first program and second program in the generated program storage unit 18.

  The write processing unit 19 converts the program language from C language to machine language based on the first program and the second program stored in the generated program storage unit 18, and then stores them in the ROM 21. On the other hand, with respect to the second program, the hardware description language program is converted into write data for writing to the logic circuit 22 and then written to the logic circuit 22.

  According to the program conversion apparatus 1 of the present example configured as described above, first, a processing program for performing a predetermined series of processes to be converted is stored in the original program storage unit 11. The processing program includes a plurality of different execution instructions, and each execution instruction is stored in association with an address in the storage unit.

  Then, when the execution processing unit 12 sequentially reads the execution instruction from the corresponding address in the original program storage unit 11 according to the execution order and executes the processing program, the processing in the execution processing unit 12 is monitored. The monitoring processing unit 13 stores the addresses of the execution instructions sequentially executed by the execution processing unit 12 in the address storage unit 14 in the order of execution.

  Thereafter, the extraction processing unit 15 confirms the arrangement based on the addresses stored in the address storage unit 14, and there are a predetermined number or more portions where the addresses are arranged in the same order and in a certain range. If it is confirmed that the number is equal to or greater than the predetermined number, the addresses of the corresponding part are extracted as they are arranged and stored in the extracted address storage unit 16. On the other hand, if it is not confirmed that there are a predetermined number or more, the above series of processing ends.

  When the address is extracted by the extraction processing unit 15, the conversion processing unit 17 converts the address into the extraction address based on the extraction address stored in the extraction address storage unit 16 and the processing program stored in the original program storage unit 11. The second program, which is a subroutine configured to sequentially execute the corresponding execution instructions in the order in which the extracted addresses are arranged, and the series of processes are executed, and the extracted address is supported in the series of processes. The first program that is a main routine configured to be executed by the second program is generated for the processing that is sequentially executed by each executed instruction, and the processing program before the conversion is generated by the first program It is converted into a new processing program comprising the program and the second program.

  Then, the first program and the second program generated by the conversion processing unit 17 are stored in the generated program storage unit 18 by the conversion processing unit 17, and the stored first program is stored by the writing processing unit 19. While being written in the ROM 21, the stored second program is written in the logic circuit 22.

  Thus, according to the program conversion apparatus 1 of the present example, when there are more than a predetermined number of portions where the addresses of the execution instructions are arranged in the same order and in a certain range, each execution of the portion is executed. A main routine configured to determine that the process executed by the instruction is a repetitive process, generate a second program in which the repetitive process is converted into a subroutine, and execute the process with the second program for the repetitive process Is automatically converted into a new processing program consisting of a first program (main routine) and a second program (subroutine), thereby generating an efficient and accurate program. Conversion processing can be performed.

  In addition, since the second program is generated as a program for operating the logic circuit 22, the program language of the generated second program is converted again into a program language corresponding to the logic circuit 22. Since it is not necessary, it is efficient and an accurate program for the logic circuit 22 can be obtained.

  In addition, since the write processing unit 19 automatically writes the first program and the second program stored in the generated program storage unit 18 in the ROM 21 and the logic circuit 22, the write processing is efficient. Can be implemented.

  As mentioned above, although one Embodiment of this invention was described, the specific aspect which this invention can take is not limited to this at all.

  For example, the program conversion apparatus 1 can also be configured as a program conversion apparatus 2 as shown in FIG. 6, and in this case, the program conversion apparatus 2 has an original program storage unit as shown in FIG. 31, an execution processing unit 32, a monitoring processing unit 33, an address storage unit 34, an extraction processing unit 35, an extraction address storage unit 36, a conversion processing unit 37, a conversion program storage unit 38 and a writing processing unit 39.

  The original program storage unit 31 stores a processing program to be converted. This processing program is, for example, a NC machine tool system control program created in a software program language such as C language and then converted into a machine language. A plurality of processing programs are configured to execute different processing contents. The subroutine and each subroutine are sequentially executed according to a predetermined order as shown in FIG. 7, and a part of each subroutine is repeatedly executed a plurality of times to perform a predetermined series of processes. Main routine. Each subroutine is stored in association with an address in the original program storage unit 31 as shown in FIG.

  The execution processing unit 32 executes a main routine stored in the original program storage unit 31 and performs a process of reading and executing the subroutine from an address in the original program storage unit 31 in which the subroutine is stored.

  The monitoring processing unit 33 monitors processing in the execution processing unit 32 and stores the addresses of subroutines sequentially executed by the execution processing unit 32 in the address storage unit 34 each time the subroutine is executed. Process. The data structure of the address stored in the address storage unit 34 is a data table as shown in FIG.

  The extraction processing unit 35 counts the number of each address based on the address stored in the address storage unit 34, and there is an address exceeding a preset number (for example, 3 or more). When it is confirmed that there is an address exceeding the set number, the address is extracted and the extracted address is stored in the extracted address storage unit 36. The preset number is appropriately set according to the processing contents of the processing program.

  For example, in the address example shown in FIG. 9, the address 3 is extracted as an address exceeding the preset number (three or more) and stored in the extracted address storage unit 36.

  The conversion processing unit 37 is a logic circuit for operating the logic circuit 22 based on the extracted address stored in the extracted address storage unit 36 and the processing program stored in the original program storage unit 31. A process for converting to a new processing program including the processing program is performed.

  Specifically, the conversion processing unit 37 first generates the main routine source code (C language) based on the processing program stored in the original program storage unit 31 and the extracted address stored in the extracted address storage unit 36. Program) and subroutine source code (C language program) corresponding to the extracted address.

  Next, the recognized source code of the subroutine is converted into a hardware description language to be converted into the logic circuit program, and the main routine is converted into the above-mentioned series of processes based on the recognized source code of the main routine. The process executed by the subroutine corresponding to the extracted address is converted into a new main routine configured to be executed by the converted logic circuit program.

  Thus, for example, the processing program executed in the execution sequence shown in FIG. 7 includes the converted logic circuit program (subroutine 3) and main routine, and the unconverted subroutines (subroutine 1, subroutine 2, subroutine 2). It is converted into a new processing program consisting of subroutine 4 and subroutine 5). Then, the conversion processing unit 37 stores the converted logic circuit program and main routine and the unconverted subroutines in the conversion program storage unit 38.

  The write processing unit 39 is based on the logic circuit program, main routine, and unconverted subroutines stored in the conversion program storage unit 38. For the main routine, the program language of the main routine is changed from C language to machine language. After being converted to the above, each unconverted subroutine is written in the ROM 21 as it is, while for the logic circuit program, the hardware description language program is converted into write data for writing in the logic circuit 22, A process of writing to the logic circuit 22 is performed.

  Even with the program conversion apparatus 2 configured as described above, when there is the subroutine address exceeding a predetermined number, the process executed by the subroutine is determined to be a repetition process, and the program for the repetition process is determined. Is converted into a logic circuit program, and the repetitive processing is converted into a new main routine that is configured to execute the processing by the logic circuit program. Since the program is automatically converted into a new processing program consisting of the converted logic circuit program and main routine and unconverted subroutines, the same effect as the program conversion apparatus 1 can be obtained.

  In the above example, the write processing units 19 and 39 execute the first program and the second program stored in the generated program storage unit 18, the logic circuit program and the main routine stored in the conversion program storage unit 38, respectively. In this configuration, the C language is converted into machine language, or the hardware description language is converted into write data for writing into the logic circuit 22 and then written into the ROM 21 or the logic circuit 22. Instead, the conversion processing units 17 and 37 generate or convert the first program and the second program, the logic circuit program, and the main routine using machine language or write data for writing to the logic circuit 22. You may comprise. In this case, the write processing units 19 and 39 are configured to write the data stored in the generated program storage unit 18 and the conversion program storage unit 38 into the ROM 21 and the logic circuit 22 as they are.

  The processing program stored in the original program storage units 11 and 31 includes a main routine including a plurality of different execution instructions and a subroutine including a plurality of different execution instructions and executing different processing contents. It may be configured. In this case, a repetitive process is extracted from the execution instruction of the main routine to generate a logic circuit program (new subroutine), or a repetitive process is extracted from the execution instruction of a certain subroutine to generate a logic circuit program ( A new subroutine) or a subroutine that is repeatedly executed can be converted into a logic circuit program.

  In the above example, each execution instruction is executed in the execution order as shown in FIG. 2 (that is, a repetitive processing unit (execution instruction 6, execution instruction 7, execution instruction 8, execution instruction 9, execution instruction 10). In addition, the repetitive processing unit of the processing program in which the execution instruction 11) is continuously repeated three times is formed as a subroutine to generate a program for the logic circuit 22, but the present invention is not limited to this, and is shown in FIG. Similarly, the execution instruction 6, execution instruction 7, execution instruction 8, execution instruction 9, and execution instruction 10 that are executed a total of three times with other execution instructions are also converted into subroutines and the program for the logic circuit 22 is executed. Can be generated.

  Furthermore, a repetitive processing unit (subroutine) of a processing program (that is, a processing program in which subroutine 3 is repeated three times in succession) in which each subroutine is executed in the execution order as shown in FIG. However, the present invention is not limited to this, and as shown in FIG. 11, the program for the logic circuit 22 is similarly applied to the subroutine 3 executed three times in total with other subroutines interposed therebetween. Can be converted.

It is the block diagram which showed schematic structure of the program conversion apparatus which concerns on one Embodiment of this invention. It is explanatory drawing which showed the execution order of each execution instruction. It is explanatory drawing which showed the data structure of the processing program stored in the original program memory | storage part of this embodiment. It is explanatory drawing which showed the data structure of the address stored in the address memory | storage part of this embodiment. It is explanatory drawing for demonstrating the processing program converted by the conversion process part of this embodiment. It is the block diagram which showed schematic structure of the program conversion apparatus which concerns on other embodiment of this invention. It is explanatory drawing which showed the execution order of each subroutine. It is explanatory drawing which showed the data structure of the processing program stored in the original program memory | storage part of other embodiment. It is explanatory drawing which showed the data structure of the address stored in the address memory | storage part of other embodiment. It is explanatory drawing which showed the execution order of each execution instruction. It is explanatory drawing which showed the execution order of each subroutine.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Program converter 11 Original program memory | storage part 12 Execution process part 13 Monitoring process part 14 Address memory | storage part 15 Extraction process part 16 Extraction address memory | storage part 17 Conversion process part 18 Generation | occurrence | production program storage part 19 Write process part 21 ROM
22 logic circuits

Claims (5)

A program for performing a series of processes including a plurality of different execution instructions, each of which is sequentially executed according to a preset order, and a part of each of the execution instructions is executed a plurality of times. Based on the processing program configured as described above, a first program as a main routine and a second program as a subroutine are generated, and the processing program is converted into a new process including the first program and the second program. A device for converting into a program,
An original program storage unit that stores the processing program before conversion, and stores each execution instruction in association with an address in the storage unit;
An execution processing unit that sequentially reads out the execution instruction from the address in the original program storage unit in which the execution instruction is stored according to the execution order, and executes the processing program;
An address storage unit for storing the address;
A monitoring processing unit that monitors processing in the execution processing unit and stores the addresses of the execution instructions sequentially executed by the execution processing unit in the address storage unit in the order in which the execution instructions are executed;
Based on the addresses stored in the address storage unit, the arrangement is confirmed, and it is confirmed whether there are more than a preset number of portions where the addresses are arranged in a certain number or more in the same order, When it is confirmed that there are more than the set number, an extraction processing unit that extracts each address of the corresponding part as it is,
Based on the address extracted by the extraction processing unit and the processing program stored in the original program storage unit, the execution instructions corresponding to the extraction address are sequentially executed in the order in which the extraction addresses are arranged. The second program and the series of processes are executed, and the processes sequentially executed by the execution instructions corresponding to the extraction addresses in the series of processes are executed by the second program. A conversion processing unit that generates the first program configured as described above and converts the processing program before conversion into a new processing program including the generated first program and second program;
A program conversion apparatus comprising: a generated program storage unit that stores a first program and a second program generated by the conversion processing unit.   The program conversion apparatus according to claim 1, wherein the conversion processing unit is configured to generate the second program as a program for operating a programmable logic circuit.   A write processing unit for writing the first program and the second program stored in the generated program storage unit into the storage device for the first program and the logic circuit for the second program; 3. The program conversion apparatus according to claim 2, wherein A processing program comprising a plurality of subroutines configured to execute different processing contents and a main routine configured to execute a series of preset processes by executing the subroutines. An apparatus for converting into a new processing program including a logic circuit program for operating a possible logic circuit,
An original program storage unit that stores the processing program before conversion, and stores each subroutine in association with an address in the storage unit;
An execution processing unit that executes a main routine stored in the original program storage unit and reads and executes the subroutine from an address in the original program storage unit in which the subroutine is stored;
An address storage unit for storing the address;
A monitoring processing unit that monitors processing in the execution processing unit and stores the address of a subroutine executed by the execution processing unit in the address storage unit each time the subroutine is executed;
Based on the address stored in the address storage unit, the number for each address is counted to check whether there is an address exceeding the preset number, and the address exceeding the set number If it is confirmed that there is, the extraction processing unit that extracts the address,
Based on the address extracted by the extraction processing unit and the processing program stored in the original program storage unit, a subroutine corresponding to the extraction address is converted into the logic circuit program, and The main routine is converted into a new main routine configured to execute the processing executed by the subroutine corresponding to the extracted address by the converted logic circuit program, and the processing program before the conversion is converted. A conversion processing unit that converts the converted logic circuit program and main routine into a new processing program including the unconverted subroutines;
A program conversion apparatus comprising: a logic circuit program converted by the conversion processing unit and a conversion program storage unit for storing at least a main routine.   A logic circuit program and a main routine stored in the conversion program storage unit; a logic processing program for the logic circuit program; and a writing processing unit for writing the main routine to the storage device. 5. The program conversion apparatus according to claim 4, wherein

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