JPS6249502A - Programmable controller - Google Patents

Abstract

PURPOSE:To increase the arithmetic processing speed and to simplify the hardware by adding the information to a sequence instruction and an operand to designate execution or non-execution of these sequence and operand. CONSTITUTION:The execution information 3C is added to an instruction code 3A of a sequence control instruction to designate execution or non-execution of this code 3A. A sequence control processor 3D fetches an instruction from a program memory and at the same time decides execution or non-execution of the instruction 3A according to the result of execution of the preceding instruction and the information 3C. Then the processor 3D fetches the next operand. When the processor 3D is unable to process the fetched instruction, an arithmetic processor 3F is started for execution of the fetched instruction. In such a way, it is possible to increase the arithmetic processing speed and to simplify the hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a programmable controller, and particularly to an improvement in a sequence program control method.

[Technical Background of the Invention and Problems thereof] Generally, a sequence program is executed by determining whether to execute the next instruction based on the execution result of the previous instruction, as shown in FIG.

Therefore, it is necessary to make the above judgment each time a sequence instruction is executed, but conventionally, after fetching an instruction, this instruction is interpreted, and if it is not executed, the address up to the next instruction, which is different for each instruction, is Jump processing is performed to find it.

Performing these processes complicates the hardware, and at the same time requires information indicating the configuration state of the operands required for each instruction, making the instruction code complex.

FIG. 4 is a time chart showing an example of a conventional sequence instruction execution process. First, in process 1A, an instruction code is fetched, and then in process 1B, it is determined whether or not to execute this instruction based on input conditions. When executing, process 1C
Move to.

If not executed, interpret the contents of the instruction fetched in step 1D and the configuration state of the operands, and then execute step 1 after the interpretation is completed.
Jump to the next command with E.

When executing in step 1C, the contents of the instruction are determined, each operand data is fetched, and then execution processing is performed.

Therefore, if sequence commands are controlled by the conventional method shown in FIG. 4, the judgment and processing when the sequence command is not executed becomes complicated, and the processing time becomes longer.

[Object of the Invention] An object of the present invention is to provide a programmable controller that adds information specifying whether or not to execute sequence instructions and operands, thereby speeding up arithmetic processing and simplifying hardware. It is said that

[Summary of the Invention] The present invention provides an instruction code in which information specifying whether or not to execute each sequence instruction and operand is added, and a sequence that controls execution or non-execution of the instruction based on the instruction code and input conditions. It is equipped with a control processor and an arithmetic processor that executes arithmetic operations when instruction execution is specified by the sequence control processor, thereby efficiently skipping instructions and operands when they are not executed, and speeding up arithmetic processing. This is a programmable controller with simplified hardware.

[Embodiments of the invention] An embodiment of the present invention is shown in FIG.

In the present invention, as shown in FIG. 1, the instruction code 3A of the sequence control instruction is provided with execution information 3C that specifies whether or not to execute the sequence control instruction, and the sequence control processor 3D fetches the instruction from the program memory and at the same time executes the execution result of the previous instruction. Then, it is determined whether the instruction 3A is to be executed based on the execution information 3C, and if the instruction 3A is not to be executed, the next operand is fetched.

At this time, execution information 3E, which is always null, is added to the operand as information specifying whether or not to execute.
Ignored when fetching.

In this way, when an instruction is not executed, the instruction after the instruction is treated as an unexecuted instruction, and since the operand is always processed as an unexecuted instruction, only 7 etches of the memory are automatically performed until the next instruction.

On the other hand, when executing the fetched instruction, the sequence control processor 3D starts the arithmetic processor 3F when it becomes unable to process it by itself, and the arithmetic processor 3F performs the arithmetic operation of the fetch instruction.

In parallel with this, the sequence control processor 3D fetches the operand 3B, ignores execution, fetches the next instruction code, and waits.

The arithmetic processor 3F returns control to the sequence control processor 3D upon completion of the arithmetic operation.

By controlling the execution of a sequence program using the above configuration, the processing when sequence instructions are not executed is shortened, and the distinction between operands and instruction codes makes it easy to skip operands without executing them. becomes possible.

[Effects of the Invention] As explained above, according to the present invention, information is added to the sequence control instruction code to determine whether the instruction, including the operand, will be executed according to the input conditions of the instruction, or whether the instruction will not execute the operand. Since the sequence control processor controls the execution/non-execution of instructions, it is possible to simplify the hardware of the sequence control processor and shorten the processing time when sequence control instructions are not executed. A rational programmable controller that performs control efficiently can be realized.

[Brief explanation of drawings]

FIG. 1 is a hardware configuration diagram of a sequence instruction showing an embodiment of the present invention, FIG. 2 is a time chart showing an instruction execution procedure in the present invention, and FIG. 3 is a diagram showing a general configuration of a sequence control instruction. , FIG. 4 is a time chart showing a conventional method of controlling execution of sequence instructions. 1A to 1E... Arithmetic process 3A... Arithmetic instruction code 3B... Operand code 3C, 3E... Execution information 3D... Sequence control processor 3F... Arithmetic processor

Claims (1)

[Claims] In a programmable controller that sequentially interprets and processes sequence instructions in a storage device, execution information that specifies whether or not to execute them is added to each sequence instruction and operand, and execution of the sequence instructions is controlled based on input conditions and the above execution information. A programmable controller comprising: a sequence control processor; and an arithmetic processor that executes calculations according to instructions from the sequence control processor.