AU2001230982A1 - Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors - Google Patents

Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors

Info

Publication number
AU2001230982A1
AU2001230982A1 AU2001230982A AU3098201A AU2001230982A1 AU 2001230982 A1 AU2001230982 A1 AU 2001230982A1 AU 2001230982 A AU2001230982 A AU 2001230982A AU 3098201 A AU3098201 A AU 3098201A AU 2001230982 A1 AU2001230982 A1 AU 2001230982A1
Authority
AU
Australia
Prior art keywords
mirrors
micro
stress
wafer bonding
bonding techniques
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001230982A
Inventor
Timothy G Slater
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xros Inc
Original Assignee
Xros Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xros Inc filed Critical Xros Inc
Publication of AU2001230982A1 publication Critical patent/AU2001230982A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
AU2001230982A 2000-01-18 2001-01-18 Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors Abandoned AU2001230982A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US17632500P 2000-01-18 2000-01-18
US60/176,325 2000-01-18
US71591600A 2000-11-16 2000-11-16
US09/715,916 2000-11-16
PCT/US2001/001758 WO2001054176A1 (en) 2000-01-18 2001-01-18 Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors

Publications (1)

Publication Number Publication Date
AU2001230982A1 true AU2001230982A1 (en) 2001-07-31

Family

ID=26872109

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001230982A Abandoned AU2001230982A1 (en) 2000-01-18 2001-01-18 Wafer bonding techniques to minimize built-in stress of silicon microstructures and micro-mirrors

Country Status (4)

Country Link
EP (1) EP1254479A1 (en)
AU (1) AU2001230982A1 (en)
CA (1) CA2397760A1 (en)
WO (1) WO2001054176A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100549866B1 (en) * 2001-08-22 2006-02-08 고려대학교 산학협력단 Pharmaceutic ingredient for medical treatment and prevention of cancer

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4580568A (en) 1984-10-01 1986-04-08 Cook, Incorporated Percutaneous endovascular stent and method for insertion thereof
NL8501773A (en) * 1985-06-20 1987-01-16 Philips Nv METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES
US4902508A (en) 1988-07-11 1990-02-20 Purdue Research Foundation Tissue graft composition
JPH05136014A (en) * 1991-11-15 1993-06-01 Sumitomo Metal Mining Co Ltd Manufacture of laminated soi substrate
JPH0774329A (en) * 1993-09-06 1995-03-17 Toshiba Corp Semiconductor device
US5629790A (en) * 1993-10-18 1997-05-13 Neukermans; Armand P. Micromachined torsional scanner
US5597410A (en) * 1994-09-15 1997-01-28 Yen; Yung C. Method to make a SOI wafer for IC manufacturing
US5554389A (en) 1995-04-07 1996-09-10 Purdue Research Foundation Urinary bladder submucosa derived tissue graft
US5733337A (en) 1995-04-07 1998-03-31 Organogenesis, Inc. Tissue repair fabric
US5755791A (en) 1996-04-05 1998-05-26 Purdue Research Foundation Perforated submucosal tissue graft constructs
WO1998022158A2 (en) 1996-08-23 1998-05-28 Cook Biotech, Incorporated Graft prosthesis, materials and methods
WO1998026291A1 (en) 1996-12-10 1998-06-18 Purdue Research Foundation Gastric submucosal tissue as a novel diagnosis tool
EP0946186B1 (en) 1996-12-10 2003-03-26 Purdue Research Foundation Stomach submucosa derived tissue graft
EP0942739B1 (en) 1996-12-10 2006-04-12 Purdue Research Foundation Biomaterial derived from vertebrate liver tissue

Also Published As

Publication number Publication date
CA2397760A1 (en) 2001-07-26
WO2001054176A9 (en) 2003-01-16
EP1254479A1 (en) 2002-11-06
WO2001054176A1 (en) 2001-07-26

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