ATE547753T1 - Einstellen der geschwindigkeit von getakteten schaltungen - Google Patents

Einstellen der geschwindigkeit von getakteten schaltungen

Info

Publication number
ATE547753T1
ATE547753T1 AT02251907T AT02251907T ATE547753T1 AT E547753 T1 ATE547753 T1 AT E547753T1 AT 02251907 T AT02251907 T AT 02251907T AT 02251907 T AT02251907 T AT 02251907T AT E547753 T1 ATE547753 T1 AT E547753T1
Authority
AT
Austria
Prior art keywords
speed
adjusting
clocked circuits
system reset
bus
Prior art date
Application number
AT02251907T
Other languages
English (en)
Inventor
Gary A Solomon
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE547753T1 publication Critical patent/ATE547753T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Control Of Electric Motors In General (AREA)
  • Electrophonic Musical Instruments (AREA)
AT02251907T 2001-03-27 2002-03-18 Einstellen der geschwindigkeit von getakteten schaltungen ATE547753T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/819,003 US6680631B2 (en) 2001-03-27 2001-03-27 Setting the speed of clocked circuitry

Publications (1)

Publication Number Publication Date
ATE547753T1 true ATE547753T1 (de) 2012-03-15

Family

ID=25226974

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02251907T ATE547753T1 (de) 2001-03-27 2002-03-18 Einstellen der geschwindigkeit von getakteten schaltungen

Country Status (5)

Country Link
US (1) US6680631B2 (de)
EP (1) EP1246044B1 (de)
AT (1) ATE547753T1 (de)
HK (1) HK1046564A1 (de)
TW (1) TWI269958B (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10055938A1 (de) * 2000-11-10 2002-05-23 Hirschmann Electronics Gmbh Datenübertragung
TW533357B (en) * 2001-12-14 2003-05-21 Via Tech Inc Method of hot switching the data transmission rate of bus
US20040177204A1 (en) * 2003-01-30 2004-09-09 Campbell David C. Bus interface with variable resistance coupling
US9779235B2 (en) * 2007-10-17 2017-10-03 Sukamo Mertoguno Cognizant engines: systems and methods for enabling program observability and controlability at instruction level granularity

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5274337A (en) * 1991-05-03 1993-12-28 Intel Corporation Clock speed limiter for a microprocessor by comparing clock signal with a predetermined frequency
US5298867A (en) * 1991-12-13 1994-03-29 Universities Research Association, Inc. Phase-locked loop with controlled phase slippage
USH1489H (en) * 1993-04-05 1995-09-05 Caterpillar Inc. System for performing a plurality of measurements
US5438599A (en) * 1993-09-30 1995-08-01 Lsi Logic Corporation Self-calibration timing circuit
US5434996A (en) * 1993-12-28 1995-07-18 Intel Corporation Synchronous/asynchronous clock net with autosense
US5450458A (en) * 1994-08-05 1995-09-12 International Business Machines Corporation Method and apparatus for phase-aligned multiple frequency synthesizer with synchronization window decoder
US5678065A (en) 1994-09-19 1997-10-14 Advanced Micro Devices, Inc. Computer system employing an enable line for selectively adjusting a peripheral bus clock frequency
JP3505018B2 (ja) * 1994-11-22 2004-03-08 株式会社ルネサステクノロジ 半導体集積回路
US6020838A (en) * 1996-12-23 2000-02-01 National Instruments Corporation System and method for generating a sigma-delta correction circuit using matrix calculation of linearity error correction coefficients
US5809291A (en) 1997-02-19 1998-09-15 International Business Machines Corp. Interoperable 33 MHz and 66 MHz devices on the same PCI bus
US5978869A (en) 1997-07-21 1999-11-02 International Business Machines Corporation Enhanced dual speed bus computer system
JP3964528B2 (ja) * 1998-03-02 2007-08-22 富士通株式会社 シリアルバス高速化回路

Also Published As

Publication number Publication date
HK1046564A1 (en) 2003-01-17
US20020171456A1 (en) 2002-11-21
TWI269958B (en) 2007-01-01
EP1246044B1 (de) 2012-02-29
US6680631B2 (en) 2004-01-20
EP1246044A1 (de) 2002-10-02

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