ATE291805T1 - Systeme, welche paketschnittstellen und paket-dma (direct memory access) schaltkreise beinhalten, um paketströme zu teilen und zusammenzusetzen - Google Patents

Systeme, welche paketschnittstellen und paket-dma (direct memory access) schaltkreise beinhalten, um paketströme zu teilen und zusammenzusetzen

Info

Publication number
ATE291805T1
ATE291805T1 AT02025688T AT02025688T ATE291805T1 AT E291805 T1 ATE291805 T1 AT E291805T1 AT 02025688 T AT02025688 T AT 02025688T AT 02025688 T AT02025688 T AT 02025688T AT E291805 T1 ATE291805 T1 AT E291805T1
Authority
AT
Austria
Prior art keywords
packet
circuits
packets
streams
circuities
Prior art date
Application number
AT02025688T
Other languages
English (en)
Inventor
Barton Sano
Laurent R Moll
Manu Gulati
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE291805T1 publication Critical patent/ATE291805T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/40—Flow control; Congestion control using split connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AT02025688T 2001-11-20 2002-11-20 Systeme, welche paketschnittstellen und paket-dma (direct memory access) schaltkreise beinhalten, um paketströme zu teilen und zusammenzusetzen ATE291805T1 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US33178901P 2001-11-20 2001-11-20
US34471301P 2001-12-24 2001-12-24
US34871702P 2002-01-14 2002-01-14
US34877702P 2002-01-14 2002-01-14
US38074002P 2002-05-15 2002-05-15
US10/270,016 US7227870B2 (en) 2001-11-20 2002-10-11 Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams

Publications (1)

Publication Number Publication Date
ATE291805T1 true ATE291805T1 (de) 2005-04-15

Family

ID=27559481

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02025688T ATE291805T1 (de) 2001-11-20 2002-11-20 Systeme, welche paketschnittstellen und paket-dma (direct memory access) schaltkreise beinhalten, um paketströme zu teilen und zusammenzusetzen

Country Status (4)

Country Link
US (2) US7227870B2 (de)
EP (1) EP1313272B1 (de)
AT (1) ATE291805T1 (de)
DE (1) DE60203358T2 (de)

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Also Published As

Publication number Publication date
US20030095559A1 (en) 2003-05-22
DE60203358T2 (de) 2006-02-09
EP1313272A1 (de) 2003-05-21
US7227870B2 (en) 2007-06-05
DE60203358D1 (de) 2005-04-28
EP1313272B1 (de) 2005-03-23
US20070291781A1 (en) 2007-12-20
US7680140B2 (en) 2010-03-16

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