ATE505870T1 - Verfahren und schaltung zum empfangen von daten - Google Patents
Verfahren und schaltung zum empfangen von datenInfo
- Publication number
- ATE505870T1 ATE505870T1 AT07849274T AT07849274T ATE505870T1 AT E505870 T1 ATE505870 T1 AT E505870T1 AT 07849274 T AT07849274 T AT 07849274T AT 07849274 T AT07849274 T AT 07849274T AT E505870 T1 ATE505870 T1 AT E505870T1
- Authority
- AT
- Austria
- Prior art keywords
- signal
- circuit
- receiver
- frequency
- receiving data
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 2
- 238000005070 sampling Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/10—Arrangements for initial synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Circuits Of Receivers In General (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06125048 | 2006-11-29 | ||
PCT/IB2007/054816 WO2008065615A1 (en) | 2006-11-29 | 2007-11-28 | Method and circuit for receiving data |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE505870T1 true ATE505870T1 (de) | 2011-04-15 |
Family
ID=39263046
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT07849274T ATE505870T1 (de) | 2006-11-29 | 2007-11-28 | Verfahren und schaltung zum empfangen von daten |
Country Status (6)
Country | Link |
---|---|
US (1) | US8433000B2 (de) |
EP (1) | EP2092681B1 (de) |
CN (1) | CN101542959B (de) |
AT (1) | ATE505870T1 (de) |
DE (1) | DE602007013934D1 (de) |
WO (1) | WO2008065615A1 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2011004580A1 (ja) * | 2009-07-06 | 2012-12-20 | パナソニック株式会社 | クロックデータリカバリ回路 |
EP2466755A1 (de) * | 2010-12-17 | 2012-06-20 | Nxp B.V. | Frequenzerfassung mit einem Trainingsmuster mit fester Randdichte |
CN104597802B (zh) * | 2014-11-28 | 2017-10-03 | 苏州工业职业技术学院 | 一种超高采样率可重现数据采集系统 |
US9992049B1 (en) * | 2016-06-17 | 2018-06-05 | Xilinx, Inc. | Numerically controlled oscillator for fractional burst clock data recovery applications |
US10277440B1 (en) * | 2016-10-24 | 2019-04-30 | Marvell International Ltd. | Determining common phase error |
CN107070595A (zh) * | 2017-02-20 | 2017-08-18 | 郑州云海信息技术有限公司 | 一种serdes数据速率自适应系统及serdes |
KR20210141813A (ko) * | 2020-05-13 | 2021-11-23 | 삼성디스플레이 주식회사 | 클록 데이터 복원 회로, 표시 장치, 및 클록 데이터 복원 회로의 구동 방법 |
US11212072B1 (en) | 2020-12-22 | 2021-12-28 | Xilinx, Inc. | Circuit for and method of processing a data stream |
CN113886300B (zh) * | 2021-09-23 | 2024-05-03 | 珠海一微半导体股份有限公司 | 一种总线接口的时钟数据自适应恢复系统及芯片 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5164965A (en) * | 1991-04-22 | 1992-11-17 | Motorola, Inc. | Method and apparatus for synchronizing a receiver to a received signal |
US5642243A (en) * | 1994-09-27 | 1997-06-24 | Cirrus Logic, Inc. | Timing recovery frequency error detector for sampled amplitude magnetic recording |
JP3956062B2 (ja) * | 1996-07-30 | 2007-08-08 | ソニー株式会社 | 再生装置および方法 |
KR100252482B1 (ko) * | 1996-12-27 | 2000-04-15 | 가시오 가즈오 | 비트동기회로 및 비트동기방법 |
US6466630B1 (en) * | 1999-01-27 | 2002-10-15 | The Johns Hopkins University | Symbol synchronization in a continuous phase modulation communications receiver |
US6907096B1 (en) * | 2000-09-29 | 2005-06-14 | Intel Corporation | Data recovery method and apparatus |
US6628212B1 (en) * | 2000-11-21 | 2003-09-30 | Nortel Networks Limited | State-driven over-sampling manchester decoder |
JP3490078B2 (ja) * | 2002-05-10 | 2004-01-26 | 沖電気工業株式会社 | ベースバンド信号受信回路及びワード検出回路 |
US7904741B2 (en) * | 2006-09-19 | 2011-03-08 | International Business Machines Corporation | Dynamic clock phase alignment between independent clock domains |
-
2007
- 2007-11-28 DE DE602007013934T patent/DE602007013934D1/de active Active
- 2007-11-28 EP EP07849274A patent/EP2092681B1/de active Active
- 2007-11-28 WO PCT/IB2007/054816 patent/WO2008065615A1/en active Application Filing
- 2007-11-28 AT AT07849274T patent/ATE505870T1/de not_active IP Right Cessation
- 2007-11-28 US US12/516,782 patent/US8433000B2/en active Active
- 2007-11-28 CN CN200780044133.7A patent/CN101542959B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US8433000B2 (en) | 2013-04-30 |
US20100172457A1 (en) | 2010-07-08 |
EP2092681B1 (de) | 2011-04-13 |
DE602007013934D1 (de) | 2011-05-26 |
EP2092681A1 (de) | 2009-08-26 |
CN101542959A (zh) | 2009-09-23 |
WO2008065615A1 (en) | 2008-06-05 |
CN101542959B (zh) | 2012-12-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |