ATE503192T1 - Parametrisches scan-register, digitale schaltung und verfahren zum prüfen einer digitalen schaltung unter verwendung eines solchen registers - Google Patents

Parametrisches scan-register, digitale schaltung und verfahren zum prüfen einer digitalen schaltung unter verwendung eines solchen registers

Info

Publication number
ATE503192T1
ATE503192T1 AT07820965T AT07820965T ATE503192T1 AT E503192 T1 ATE503192 T1 AT E503192T1 AT 07820965 T AT07820965 T AT 07820965T AT 07820965 T AT07820965 T AT 07820965T AT E503192 T1 ATE503192 T1 AT E503192T1
Authority
AT
Austria
Prior art keywords
register
digital circuit
parametric
testing
output
Prior art date
Application number
AT07820965T
Other languages
English (en)
Inventor
Olivier Heron
Yannick Bonhomme
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE503192T1 publication Critical patent/ATE503192T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
AT07820965T 2006-10-06 2007-10-05 Parametrisches scan-register, digitale schaltung und verfahren zum prüfen einer digitalen schaltung unter verwendung eines solchen registers ATE503192T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0608798A FR2906891B1 (fr) 2006-10-06 2006-10-06 Registre scan parametrique, circuit numerique et procede de test d'un circuit numerique a l'aide d'un tel registre
PCT/EP2007/060591 WO2008040798A1 (fr) 2006-10-06 2007-10-05 Registre scan parametrique, circuit numerique et procede de test d'un circuit numerique a l'aide d'un tel registre

Publications (1)

Publication Number Publication Date
ATE503192T1 true ATE503192T1 (de) 2011-04-15

Family

ID=38353769

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07820965T ATE503192T1 (de) 2006-10-06 2007-10-05 Parametrisches scan-register, digitale schaltung und verfahren zum prüfen einer digitalen schaltung unter verwendung eines solchen registers

Country Status (7)

Country Link
US (1) US20100293425A1 (de)
EP (1) EP2069814B1 (de)
JP (1) JP2010506161A (de)
AT (1) ATE503192T1 (de)
DE (1) DE602007013428D1 (de)
FR (1) FR2906891B1 (de)
WO (1) WO2008040798A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8140923B2 (en) * 2009-04-09 2012-03-20 Lsi Corporation Test circuit and method for testing of infant mortality related defects

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4130329B2 (ja) * 2002-04-18 2008-08-06 松下電器産業株式会社 スキャンパス回路および当該スキャンパス回路を備えた半導体集積回路
WO2003093843A1 (en) * 2002-05-01 2003-11-13 Logicvision(Canada), Inc Circuit and method for adding parametric test capability to digital boundary scan

Also Published As

Publication number Publication date
WO2008040798A1 (fr) 2008-04-10
FR2906891B1 (fr) 2008-12-19
EP2069814B1 (de) 2011-03-23
JP2010506161A (ja) 2010-02-25
DE602007013428D1 (de) 2011-05-05
US20100293425A1 (en) 2010-11-18
EP2069814A1 (de) 2009-06-17
FR2906891A1 (fr) 2008-04-11

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties