ATE500611T1 - Verfahren zum aufteilen eines substrats - Google Patents

Verfahren zum aufteilen eines substrats

Info

Publication number
ATE500611T1
ATE500611T1 AT08843202T AT08843202T ATE500611T1 AT E500611 T1 ATE500611 T1 AT E500611T1 AT 08843202 T AT08843202 T AT 08843202T AT 08843202 T AT08843202 T AT 08843202T AT E500611 T1 ATE500611 T1 AT E500611T1
Authority
AT
Austria
Prior art keywords
substrate
splitting
periphery
wave
sector
Prior art date
Application number
AT08843202T
Other languages
English (en)
Inventor
Mohamed Nadia Ben
Sebastien Kerdiles
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE500611T1 publication Critical patent/ATE500611T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Dicing (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
AT08843202T 2007-10-23 2008-10-21 Verfahren zum aufteilen eines substrats ATE500611T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0758502A FR2922681A1 (fr) 2007-10-23 2007-10-23 Procede de detachement d'un substrat.
PCT/EP2008/064200 WO2009053355A1 (en) 2007-10-23 2008-10-21 Method of splitting a substrate

Publications (1)

Publication Number Publication Date
ATE500611T1 true ATE500611T1 (de) 2011-03-15

Family

ID=39586966

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08843202T ATE500611T1 (de) 2007-10-23 2008-10-21 Verfahren zum aufteilen eines substrats

Country Status (9)

Country Link
US (1) US8003493B2 (de)
EP (1) EP2212910B1 (de)
JP (1) JP5519516B2 (de)
KR (1) KR101490779B1 (de)
CN (1) CN101836287B (de)
AT (1) ATE500611T1 (de)
DE (1) DE602008005350D1 (de)
FR (1) FR2922681A1 (de)
WO (1) WO2009053355A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8570514B2 (en) * 2011-06-20 2013-10-29 Kla-Tencor Corporation Optical system polarizer calibration
JP6213046B2 (ja) * 2013-08-21 2017-10-18 信越半導体株式会社 貼り合わせウェーハの製造方法
FR3036845B1 (fr) * 2015-05-28 2017-05-26 Soitec Silicon On Insulator Procede de transfert d'une couche d'un substrat monocristallin

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3901423A (en) 1973-11-26 1975-08-26 Purdue Research Foundation Method for fracturing crystalline materials
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
FR2725074B1 (fr) 1994-09-22 1996-12-20 Commissariat Energie Atomique Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat
CN1132223C (zh) 1995-10-06 2003-12-24 佳能株式会社 半导体衬底及其制造方法
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
CA2233127C (en) * 1997-03-27 2004-07-06 Canon Kabushiki Kaisha Method and apparatus for separating composite member using fluid
US6245161B1 (en) 1997-05-12 2001-06-12 Silicon Genesis Corporation Economical silicon-on-silicon hybrid wafer assembly
JP2003163335A (ja) 2001-11-27 2003-06-06 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
FR2834820B1 (fr) 2002-01-16 2005-03-18 Procede de clivage de couches d'une tranche de materiau
EP1588416B1 (de) 2003-01-07 2009-03-25 S.O.I.Tec Silicon on Insulator Technologies Recycling eines wafers mit einer mehrschichtstruktur nach dem abnehmen einer dünnen schicht
US7235138B2 (en) 2003-08-21 2007-06-26 Micron Technology, Inc. Microfeature workpiece processing apparatus and methods for batch deposition of materials on microfeature workpieces
US20050217560A1 (en) * 2004-03-31 2005-10-06 Tolchinsky Peter G Semiconductor wafers with non-standard crystal orientations and methods of manufacturing the same

Also Published As

Publication number Publication date
EP2212910A1 (de) 2010-08-04
JP2011501452A (ja) 2011-01-06
FR2922681A1 (fr) 2009-04-24
EP2212910B1 (de) 2011-03-02
DE602008005350D1 (de) 2011-04-14
US20100176493A1 (en) 2010-07-15
KR101490779B1 (ko) 2015-02-09
CN101836287B (zh) 2012-12-05
US8003493B2 (en) 2011-08-23
JP5519516B2 (ja) 2014-06-11
WO2009053355A1 (en) 2009-04-30
CN101836287A (zh) 2010-09-15
KR20100072010A (ko) 2010-06-29

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties