ATE49680T1 - Verfahren zum herstellen eines gekapselten icpl|ttchens. - Google Patents

Verfahren zum herstellen eines gekapselten icpl|ttchens.

Info

Publication number
ATE49680T1
ATE49680T1 AT85104411T AT85104411T ATE49680T1 AT E49680 T1 ATE49680 T1 AT E49680T1 AT 85104411 T AT85104411 T AT 85104411T AT 85104411 T AT85104411 T AT 85104411T AT E49680 T1 ATE49680 T1 AT E49680T1
Authority
AT
Austria
Prior art keywords
chip
encapsulated
leads
support
making
Prior art date
Application number
AT85104411T
Other languages
English (en)
Inventor
Thomas G Gilder Jr
Raymond D O'dean
Original Assignee
Gte Prod Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gte Prod Corp filed Critical Gte Prod Corp
Application granted granted Critical
Publication of ATE49680T1 publication Critical patent/ATE49680T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Credit Cards Or The Like (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
AT85104411T 1984-05-02 1985-04-11 Verfahren zum herstellen eines gekapselten icpl|ttchens. ATE49680T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60631084A 1984-05-02 1984-05-02
EP85104411A EP0163081B1 (de) 1984-05-02 1985-04-11 Verfahren zum Herstellen eines gekapselten IC-Plättchens

Publications (1)

Publication Number Publication Date
ATE49680T1 true ATE49680T1 (de) 1990-02-15

Family

ID=24427458

Family Applications (1)

Application Number Title Priority Date Filing Date
AT85104411T ATE49680T1 (de) 1984-05-02 1985-04-11 Verfahren zum herstellen eines gekapselten icpl|ttchens.

Country Status (5)

Country Link
EP (1) EP0163081B1 (de)
JP (1) JPS60240133A (de)
KR (1) KR850008047A (de)
AT (1) ATE49680T1 (de)
DE (1) DE3575497D1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960000793B1 (ko) * 1993-04-07 1996-01-12 삼성전자주식회사 노운 굳 다이 어레이 및 그 제조방법
US7646658B2 (en) * 2007-05-31 2010-01-12 Qualcomm Incorporated Memory device with delay tracking for improved timing margin

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4137546A (en) * 1977-10-14 1979-01-30 Plessey Incorporated Stamped lead frame for semiconductor packages
JPS5521128A (en) * 1978-08-02 1980-02-15 Hitachi Ltd Lead frame used for semiconductor device and its assembling
FR2462024A1 (fr) * 1979-07-17 1981-02-06 Thomson Csf Plate-forme support de grille de connexion, notamment pour boitier de circuits integres, et boitier comportant une telle plate-forme
JPS56137658A (en) * 1980-03-31 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device

Also Published As

Publication number Publication date
KR850008047A (ko) 1985-12-11
EP0163081B1 (de) 1990-01-17
DE3575497D1 (de) 1990-02-22
EP0163081A1 (de) 1985-12-04
JPS60240133A (ja) 1985-11-29

Similar Documents

Publication Publication Date Title
ATE59733T1 (de) Ein verfahren zum herstellen einer halbleiteranordnung mit leiter-steckerstiften.
DE3888895D1 (de) Verfahren zum elektrischen Verbinden von integrierten Schaltungschips, eine Harzzusammensetzung für Podeste, und gemäss diesem Verfahren hergestellte Flüssigkristallanzeigevorrichtung.
DE3786914D1 (de) Verfahren zum herstellen einer integrierten schaltungspackungsstruktur.
EP0257681A3 (de) Verfahren zur Herstellung von in Kunststoff eingeschmolzenen Halbleiterbauelementen und damit hergestellte Bauelemente
DE3381509D1 (de) Verfahren zum herstellen von halbleiteranordnungen.
JPS57207356A (en) Semiconductor device
IT1027550B (it) Apparecchiatura per provare assiemi circuitali lugici
IT7926078A0 (it) Apparecchiatura per provare macrostrutture su chip lsi.
AT377890B (de) Verfahren und vorrichtung zum herstellen von elektrischen schaltungsverdrahtungen
AT389184B (de) Vorrichtung zum herstellen von kompaktleitungen
ATE4757T1 (de) Montierungsanordnung eines integrierten schaltungschips und verfahren zum herstellen einer solchen anordnung.
JPS56125864A (en) Device for bonding tape to and testing integrated circuit chip and method therefor
BR7605354A (pt) Conjunto semicondutor encapsulado e passivado e processo de fabrica-lo
DE3772490D1 (de) Halbleiteranordnung sowie verfahren zum herstellen und testen derselben.
KR880700275A (ko) 전자 장치 테스트 방법 및 테스트용 집적 회로 테스터
ATE49680T1 (de) Verfahren zum herstellen eines gekapselten icpl|ttchens.
DE3887770D1 (de) Verfahren und Apparat zum Verbinden von Leiterdrähten für eine integrierte Schaltungsanordnung.
ES2011542A6 (es) Comprobador de cortocircuitos en bastidores de montaje de conductores, y metodo para comprobar una capsula de circuito.
DE3761175D1 (de) Verfahren zur zugspruefung von drahtverbindungen in halbleitermikrogeraeten.
DE3888511D1 (de) Verfahren zum Herstellen von elektrischen Kontakten in integrierten Schaltungen.
ATA120788A (de) Verfahren zum herstellen von elektrisch leitfähigen polymer-metallverbindungen
ATE45837T1 (de) Verfahren zur herstellung eines leiterrahmentraegers fuer ein ic-plaettchen.
DE68928308D1 (de) Verfahren zum Herstellen von integrierten Halbleiterschaltungen in der Universalschaltkreistechnik
ATE48205T1 (de) Verfahren zum herstellen eines in einem gehaeuse montierten ic-plaettchens.
DE69030411D1 (de) Leiterrahmen für Halbleiteranordnung

Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee