ATE484793T1 - Multithread eingebetteter prozessor mit ein- ausgabe fähigkeit - Google Patents

Multithread eingebetteter prozessor mit ein- ausgabe fähigkeit

Info

Publication number
ATE484793T1
ATE484793T1 AT02717906T AT02717906T ATE484793T1 AT E484793 T1 ATE484793 T1 AT E484793T1 AT 02717906 T AT02717906 T AT 02717906T AT 02717906 T AT02717906 T AT 02717906T AT E484793 T1 ATE484793 T1 AT E484793T1
Authority
AT
Austria
Prior art keywords
threads
embedded processor
processor
multithread
input
Prior art date
Application number
AT02717906T
Other languages
English (en)
Inventor
Jason Gosior
Colin Broughton
Phillip Jacobsen
John Sobota
Original Assignee
Eleven Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eleven Engineering Inc filed Critical Eleven Engineering Inc
Application granted granted Critical
Publication of ATE484793T1 publication Critical patent/ATE484793T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016Decoding the operand specifier, e.g. specifier format
    • G06F9/30167Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/20Pc systems
    • G05B2219/22Pc multi processor system
    • G05B2219/2214Multicontrollers, multimicrocomputers, multiprocessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Control By Computers (AREA)
  • Peptides Or Proteins (AREA)
AT02717906T 2001-04-26 2002-04-10 Multithread eingebetteter prozessor mit ein- ausgabe fähigkeit ATE484793T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/843,178 US7320065B2 (en) 2001-04-26 2001-04-26 Multithread embedded processor with input/output capability
PCT/CA2002/000488 WO2002088940A1 (en) 2001-04-26 2002-04-10 Multithread embedded processor with input/output capability

Publications (1)

Publication Number Publication Date
ATE484793T1 true ATE484793T1 (de) 2010-10-15

Family

ID=25289259

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02717906T ATE484793T1 (de) 2001-04-26 2002-04-10 Multithread eingebetteter prozessor mit ein- ausgabe fähigkeit

Country Status (6)

Country Link
US (1) US7320065B2 (de)
EP (1) EP1386227B1 (de)
JP (1) JP4101659B2 (de)
AT (1) ATE484793T1 (de)
DE (1) DE60237970D1 (de)
WO (1) WO2002088940A1 (de)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6976239B1 (en) * 2001-06-12 2005-12-13 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US7251814B2 (en) * 2001-08-24 2007-07-31 International Business Machines Corporation Yield on multithreaded processors
US7398374B2 (en) * 2002-02-27 2008-07-08 Hewlett-Packard Development Company, L.P. Multi-cluster processor for processing instructions of one or more instruction threads
US7334086B2 (en) * 2002-10-08 2008-02-19 Rmi Corporation Advanced processor with system on a chip interconnect technology
US9088474B2 (en) * 2002-10-08 2015-07-21 Broadcom Corporation Advanced processor with interfacing messaging network to a CPU
US7281075B2 (en) * 2003-04-24 2007-10-09 International Business Machines Corporation Virtualization of a global interrupt queue
US7065635B1 (en) * 2003-12-17 2006-06-20 Sun Microsystems, Inc. Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processor
US7802255B2 (en) * 2003-12-19 2010-09-21 Stmicroelectronics, Inc. Thread execution scheduler for multi-processing system and method
US8566828B2 (en) * 2003-12-19 2013-10-22 Stmicroelectronics, Inc. Accelerator for multi-processing system and method
US7165229B1 (en) * 2004-05-24 2007-01-16 Altera Corporation Generating optimized and secure IP cores
US7827555B2 (en) * 2004-09-13 2010-11-02 Integrated Device Technology, Inc. Scheduler for a multiprocessing computing system
US7634774B2 (en) * 2004-09-13 2009-12-15 Integrated Device Technology, Inc. System and method of scheduling computing threads
US7620821B1 (en) * 2004-09-13 2009-11-17 Sun Microsystems, Inc. Processor including general-purpose and cryptographic functionality in which cryptographic operations are visible to user-specified software
US7711955B1 (en) 2004-09-13 2010-05-04 Oracle America, Inc. Apparatus and method for cryptographic key expansion
US7426648B2 (en) * 2004-09-30 2008-09-16 Intel Corporation Global and pseudo power state management for multiple processing elements
US7373447B2 (en) * 2004-11-09 2008-05-13 Toshiba America Electronic Components, Inc. Multi-port processor architecture with bidirectional interfaces between busses
JP3866749B2 (ja) * 2005-03-07 2007-01-10 富士通株式会社 マイクロプロセッサ
US7882505B2 (en) * 2005-03-25 2011-02-01 Oracle America, Inc. Method and apparatus for switching between per-thread and per-processor resource pools in multi-threaded programs
GB0509738D0 (en) 2005-05-12 2005-06-22 Cambridge Consultants Processor and interface
CN100349121C (zh) * 2005-07-08 2007-11-14 北京中星微电子有限公司 嵌入式并行计算系统以及嵌入式并行计算方法
US7949860B2 (en) * 2005-11-25 2011-05-24 Panasonic Corporation Multi thread processor having dynamic reconfiguration logic circuit
US7730280B2 (en) * 2006-06-15 2010-06-01 Vicore Technologies, Inc. Methods and apparatus for independent processor node operations in a SIMD array processor
DE102006040416A1 (de) * 2006-08-29 2008-03-20 Siemens Ag Einrichtung zur Steuerung und/oder Regelung einer Maschine
CN101170416B (zh) * 2006-10-26 2012-01-04 阿里巴巴集团控股有限公司 网络数据存储系统及其数据访问方法
US7574679B1 (en) 2006-11-16 2009-08-11 Altera Corporation Generating cores using secure scripts
US7627706B2 (en) * 2007-09-06 2009-12-01 Intel Corporation Creation of logical APIC ID with cluster ID and intra-cluster ID
US7779233B2 (en) * 2007-10-23 2010-08-17 International Business Machines Corporation System and method for implementing a software-supported thread assist mechanism for a microprocessor
US9395983B2 (en) * 2008-08-20 2016-07-19 Freescale Semiconductor, Inc. Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation
US20100049956A1 (en) * 2008-08-20 2010-02-25 Moyer William C Debug instruction for use in a multi-threaded data processing system
KR101014028B1 (ko) * 2008-11-26 2011-02-14 한양대학교 산학협력단 고속 블록 입출력을 위한 적응성 문맥전환 방법 및 장치
US8812796B2 (en) 2009-06-26 2014-08-19 Microsoft Corporation Private memory regions and coherence optimizations
US8370577B2 (en) 2009-06-26 2013-02-05 Microsoft Corporation Metaphysically addressed cache metadata
US8356166B2 (en) * 2009-06-26 2013-01-15 Microsoft Corporation Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers
US8250331B2 (en) 2009-06-26 2012-08-21 Microsoft Corporation Operating system virtual memory management for hardware transactional memory
US20100332768A1 (en) * 2009-06-26 2010-12-30 Microsoft Corporation Flexible read- and write-monitored and buffered memory blocks
US8489864B2 (en) * 2009-06-26 2013-07-16 Microsoft Corporation Performing escape actions in transactions
US8229907B2 (en) * 2009-06-30 2012-07-24 Microsoft Corporation Hardware accelerated transactional memory system with open nested transactions
US8549523B2 (en) 2009-11-23 2013-10-01 International Business Machines Corporation Performing runtime analysis and control of folding identified threads by assuming context of another thread and executing in lieu of another thread folding tool
US8832663B2 (en) 2009-11-23 2014-09-09 International Business Machines Corporation Thread serialization and disablement tool
US8402218B2 (en) 2009-12-15 2013-03-19 Microsoft Corporation Efficient garbage collection and exception handling in a hardware accelerated transactional memory system
US9092253B2 (en) * 2009-12-15 2015-07-28 Microsoft Technology Licensing, Llc Instrumentation of hardware assisted transactional memory system
US8533440B2 (en) 2009-12-15 2013-09-10 Microsoft Corporation Accelerating parallel transactions using cache resident transactions
US8539465B2 (en) * 2009-12-15 2013-09-17 Microsoft Corporation Accelerating unbounded memory transactions using nested cache resident transactions
US9367462B2 (en) 2009-12-29 2016-06-14 Empire Technology Development Llc Shared memories for energy efficient multi-core processors
IL225988A (en) * 2013-04-28 2017-12-31 Technion Res & Development Found Ltd Multi-process based management from Meristor
US10398441B2 (en) 2013-12-20 2019-09-03 Terumo Corporation Vascular occlusion
US10680957B2 (en) * 2014-05-28 2020-06-09 Cavium International Method and apparatus for analytics in a network switch
JP6960479B2 (ja) * 2017-03-14 2021-11-05 アズールエンジン テクノロジーズ ヂュハイ インク.Azurengine Technologies Zhuhai Inc. 再構成可能並列処理
CN110996805B (zh) 2017-05-25 2024-03-19 泰尔茂株式会社 粘合封堵系统
JP6911544B2 (ja) * 2017-06-02 2021-07-28 富士通株式会社 プログラム、情報処理装置及び情報処理方法
CN108958896A (zh) * 2018-06-16 2018-12-07 温州职业技术学院 多线程并发处理系统及方法
US11564692B2 (en) 2018-11-01 2023-01-31 Terumo Corporation Occlusion systems
GB2596872B (en) * 2020-07-10 2022-12-14 Graphcore Ltd Handling injected instructions in a processor

Family Cites Families (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4155115A (en) * 1977-12-30 1979-05-15 Honeywell Inc. Process control system with analog output control circuit
US4646236A (en) 1981-04-17 1987-02-24 International Business Machines Corp. Pipelined control apparatus with multi-process address storage
US4556951A (en) * 1982-06-06 1985-12-03 Digital Equipment Corporation Central processor with instructions for processing sequences of characters
US4594655A (en) 1983-03-14 1986-06-10 International Business Machines Corporation (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions
US4636942A (en) 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
US4901230A (en) 1983-04-25 1990-02-13 Cray Research, Inc. Computer vector multiprocessing control with multiple access memory and priority conflict resolution method
JPS6370343A (ja) 1986-09-11 1988-03-30 Mitsubishi Electric Corp マイクロコンピユ−タ
JPS63100539A (ja) 1986-10-16 1988-05-02 Nippon Telegr & Teleph Corp <Ntt> パイプライン処理方式
JPS6432379A (en) 1987-07-29 1989-02-02 Hitachi Ltd Computer
EP0473714A1 (de) 1989-05-26 1992-03-11 Massachusetts Institute Of Technology Paralleles vielfaden-datenverarbeitungssystem
US5353418A (en) 1989-05-26 1994-10-04 Massachusetts Institute Of Technology System storing thread descriptor identifying one of plural threads of computation in storage only when all data for operating on thread is ready and independently of resultant imperative processing of thread
JP2967999B2 (ja) 1989-07-06 1999-10-25 富士通株式会社 プロセスの実行多重度制御処理装置
US5471593A (en) 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
US5276847A (en) 1990-02-14 1994-01-04 Intel Corporation Method for locking and unlocking a computer address
US5734921A (en) 1990-11-13 1998-03-31 International Business Machines Corporation Advanced parallel array processor computer package
US5713037A (en) 1990-11-13 1998-01-27 International Business Machines Corporation Slide bus communication functions for SIMD/MIMD array processor
US5765011A (en) 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5966528A (en) 1990-11-13 1999-10-12 International Business Machines Corporation SIMD/MIMD array processor with vector processing
US5828894A (en) 1990-11-13 1998-10-27 International Business Machines Corporation Array processor having grouping of SIMD pickets
US5404553A (en) 1991-01-09 1995-04-04 Mitsubishi Denki Kabushiki Kaisha Microprocessor and data flow microprocessor having vector operation function
US5430850A (en) 1991-07-22 1995-07-04 Massachusetts Institute Of Technology Data processing system with synchronization coprocessor for multiple threads
US5357617A (en) 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
US5404469A (en) 1992-02-25 1995-04-04 Industrial Technology Research Institute Multi-threaded microprocessor architecture utilizing static interleaving
US5546593A (en) 1992-05-18 1996-08-13 Matsushita Electric Industrial Co., Ltd. Multistream instruction processor able to reduce interlocks by having a wait state for an instruction stream
US5784552A (en) * 1993-07-28 1998-07-21 Digital Equipment Corporation Debugging a computer program by simulating execution forwards and backwards in a main history log and alternative history logs
US5632032A (en) 1994-02-07 1997-05-20 International Business Machines Corporation Cross address space thread control in a multithreaded environment
US5721920A (en) 1994-08-05 1998-02-24 Telefonaktiebolaget Lm Ericsson Method and system for providing a state oriented and event driven environment
JP2684993B2 (ja) 1994-08-10 1997-12-03 日本電気株式会社 プロセッサシステムとその制御方法
US5845331A (en) 1994-09-28 1998-12-01 Massachusetts Institute Of Technology Memory system including guarded pointers
JP3169779B2 (ja) 1994-12-19 2001-05-28 日本電気株式会社 マルチスレッドプロセッサ
US6138140A (en) 1995-07-14 2000-10-24 Sony Corporation Data processing method and device
US5867725A (en) 1996-03-21 1999-02-02 International Business Machines Corporation Concurrent multitasking in a uniprocessor
GB2311882B (en) 1996-04-04 2000-08-09 Videologic Ltd A data processing management system
US5944816A (en) 1996-05-17 1999-08-31 Advanced Micro Devices, Inc. Microprocessor configured to execute multiple threads including interrupt service routines
US5933627A (en) * 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
KR100500002B1 (ko) 1996-08-27 2005-09-08 마츠시타 덴끼 산교 가부시키가이샤 복수의명령흐름을독립적으로처리하고,명령흐름단위로처리성능을유연하게제어하는멀티스레드프로세서
US6088788A (en) 1996-12-27 2000-07-11 International Business Machines Corporation Background completion of instruction and associated fetch request in a multithread processor
US6073159A (en) 1996-12-31 2000-06-06 Compaq Computer Corporation Thread properties attribute vector based thread selection in multithreading processor
US5872963A (en) 1997-02-18 1999-02-16 Silicon Graphics, Inc. Resumption of preempted non-privileged threads with no kernel intervention
US5835705A (en) 1997-03-11 1998-11-10 International Business Machines Corporation Method and system for performance per-thread monitoring in a multithreaded processor
US5907702A (en) 1997-03-28 1999-05-25 International Business Machines Corporation Method and apparatus for decreasing thread switch latency in a multithread processor
US5903899A (en) 1997-04-23 1999-05-11 Sun Microsystems, Inc. System and method for assisting exact Garbage collection by segregating the contents of a stack into sub stacks
JPH1139209A (ja) 1997-07-07 1999-02-12 Internatl Business Mach Corp <Ibm> コンピュータ資源アクセス制御装置およびその方法
US6076157A (en) 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6105051A (en) 1997-10-23 2000-08-15 International Business Machines Corporation Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor
US6195748B1 (en) 1997-11-26 2001-02-27 Compaq Computer Corporation Apparatus for sampling instruction execution information in a processor pipeline
US6000044A (en) 1997-11-26 1999-12-07 Digital Equipment Corporation Apparatus for randomly sampling instructions in a processor pipeline
US6092180A (en) 1997-11-26 2000-07-18 Digital Equipment Corporation Method for measuring latencies by randomly selected sampling of the instructions while the instruction are executed
US6163840A (en) 1997-11-26 2000-12-19 Compaq Computer Corporation Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline
US6148396A (en) 1997-11-26 2000-11-14 Compaq Computer Corporation Apparatus for sampling path history in a processor pipeline
US5923872A (en) 1997-11-26 1999-07-13 Digital Equipment Corporation Apparatus for sampling instruction operand or result values in a processor pipeline
US6182210B1 (en) 1997-12-16 2001-01-30 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
US6018759A (en) 1997-12-22 2000-01-25 International Business Machines Corporation Thread switch tuning tool for optimal performance in a computer processor
US6298431B1 (en) * 1997-12-31 2001-10-02 Intel Corporation Banked shadowed register file
US6134653A (en) 1998-04-22 2000-10-17 Transwitch Corp. RISC processor architecture with high performance context switching in which one context can be loaded by a co-processor while another context is being accessed by an arithmetic logic unit
US6272616B1 (en) * 1998-06-17 2001-08-07 Agere Systems Guardian Corp. Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
US6154832A (en) 1998-12-04 2000-11-28 Advanced Micro Devices, Inc. Processor employing multiple register sets to eliminate interrupts
US6507862B1 (en) 1999-05-11 2003-01-14 Sun Microsystems, Inc. Switching method in a multi-threaded processor
US6341347B1 (en) 1999-05-11 2002-01-22 Sun Microsystems, Inc. Thread switch logic in a multiple-thread processor
US6438671B1 (en) * 1999-07-01 2002-08-20 International Business Machines Corporation Generating partition corresponding real address in partitioned mode supporting system
GB2355085A (en) * 1999-10-05 2001-04-11 Sharp Kk Translating a source operation to a target operation
US6357016B1 (en) * 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor

Also Published As

Publication number Publication date
DE60237970D1 (de) 2010-11-25
WO2002088940A1 (en) 2002-11-07
US7320065B2 (en) 2008-01-15
US20030093655A1 (en) 2003-05-15
EP1386227A1 (de) 2004-02-04
JP2004525468A (ja) 2004-08-19
EP1386227B1 (de) 2010-10-13
JP4101659B2 (ja) 2008-06-18

Similar Documents

Publication Publication Date Title
ATE484793T1 (de) Multithread eingebetteter prozessor mit ein- ausgabe fähigkeit
WO2003003237A3 (en) System on chip architecture
US8799929B2 (en) Method and apparatus for bandwidth allocation mode switching based on relative priorities of the bandwidth allocation modes
WO2000033185A3 (en) A multiple-thread processor for threaded software applications
WO2002073336A3 (en) Microprocessor employing a performance throttling mechanism for power management
US7941643B2 (en) Multi-thread processor with multiple program counters
US20070074004A1 (en) Systems and methods for selectively decoupling a parallel extended instruction pipeline
US7774585B2 (en) Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation
WO2001086415A3 (en) Priority in a portable thread environment
EP1376352A3 (de) Spin-Aufgabe in multi-threaded Systemen
WO2003058418A3 (en) Multiple mode power throttle mechanism
WO2008021434A1 (en) Instruction dispatching method and apparatus
EP1573532A2 (de) Architektur zur unterstüzung von mehreren gleichzeitigen verarbeitungskontexten auf einem prozessor
EP1416376A3 (de) Multithread eingebetteter Prozessor mit deterministischem Befehlsspeicher
WO2001086418A3 (en) Portable thread environment
CN100392585C (zh) 动态指令相依性监视及控制的方法与系统
EP1623318B1 (de) Rechnersystem mit parallelität auf befehls- und draht-ebene
WO2002046920A3 (en) Multi-cycle instructions
US7831979B2 (en) Processor with instruction-based interrupt handling
US20050149931A1 (en) Multithread processor architecture for triggered thread switching without any cycle time loss, and without any switching program command
US10437598B2 (en) Method and apparatus for selecting among a plurality of instruction sets to a microprocessor
US20050229018A1 (en) Configurable processor
ATE521032T1 (de) Computerbefehl mit befehlsabruf-steuerbit
US7904703B1 (en) Method and apparatus for idling and waking threads by a multithread processor
US7434039B2 (en) Computer processor capable of responding with comparable efficiency to both software-state-independent and state-dependent events

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties