ATE475103T1 - Vorrichtung zum evaluieren einer verzögerung einer eingangs-/ausgangsschaltung - Google Patents
Vorrichtung zum evaluieren einer verzögerung einer eingangs-/ausgangsschaltungInfo
- Publication number
- ATE475103T1 ATE475103T1 AT06842580T AT06842580T ATE475103T1 AT E475103 T1 ATE475103 T1 AT E475103T1 AT 06842580 T AT06842580 T AT 06842580T AT 06842580 T AT06842580 T AT 06842580T AT E475103 T1 ATE475103 T1 AT E475103T1
- Authority
- AT
- Austria
- Prior art keywords
- input
- output circuit
- buffer
- inv
- electronic device
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05112655 | 2005-12-21 | ||
PCT/IB2006/054919 WO2007072398A2 (en) | 2005-12-21 | 2006-12-18 | Method of evaluating a delay of an input/output circuit and corresponding device |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE475103T1 true ATE475103T1 (de) | 2010-08-15 |
Family
ID=38110760
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT06842580T ATE475103T1 (de) | 2005-12-21 | 2006-12-18 | Vorrichtung zum evaluieren einer verzögerung einer eingangs-/ausgangsschaltung |
Country Status (7)
Country | Link |
---|---|
US (1) | US7772875B2 (de) |
EP (1) | EP1977261B1 (de) |
JP (1) | JP2009521124A (de) |
CN (1) | CN101341417A (de) |
AT (1) | ATE475103T1 (de) |
DE (1) | DE602006015703D1 (de) |
WO (1) | WO2007072398A2 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102169515B (zh) * | 2010-02-26 | 2014-04-16 | 国际商业机器公司 | 一种专用集成电路中时钟树延迟时间的估计方法和系统 |
EP2608411B1 (de) | 2011-12-22 | 2020-03-11 | Nxp B.V. | Schaltkreis |
CN111077438B (zh) * | 2018-10-22 | 2021-11-12 | 中芯国际集成电路制造(北京)有限公司 | I/o接口延迟时间测试电路 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4795964A (en) * | 1986-08-01 | 1989-01-03 | Texas Instruments Incorporated | Method and apparatus for measuring the capacitance of complementary field-effect transistor devices |
JPH01240878A (ja) * | 1988-03-23 | 1989-09-26 | Fujitsu Ltd | 集積回路の評価装置 |
US5448181A (en) * | 1992-11-06 | 1995-09-05 | Xilinx, Inc. | Output buffer circuit having reduced switching noise |
US5438278A (en) * | 1993-09-28 | 1995-08-01 | Advanced Micro Devices, Inc. | High speed CMOS output buffer circuit minimizes propagation delay and crowbar current |
JP3311133B2 (ja) * | 1994-02-16 | 2002-08-05 | 株式会社東芝 | 出力回路 |
US6236237B1 (en) * | 1998-02-27 | 2001-05-22 | Altera Corporation | Output buffer predriver with edge compensation |
JP2000183719A (ja) * | 1998-12-11 | 2000-06-30 | Nec Corp | 入力回路、出力回路及び入出力回路、並びに該入出力回路を備えた信号伝送システム |
JP2001091568A (ja) * | 1999-09-17 | 2001-04-06 | Advantest Corp | 半導体集積回路の試験装置及び試験方法 |
JP3487281B2 (ja) * | 2000-10-18 | 2004-01-13 | セイコーエプソン株式会社 | 半導体装置及びそのテスト方法 |
-
2006
- 2006-12-18 AT AT06842580T patent/ATE475103T1/de not_active IP Right Cessation
- 2006-12-18 WO PCT/IB2006/054919 patent/WO2007072398A2/en active Application Filing
- 2006-12-18 EP EP06842580A patent/EP1977261B1/de active Active
- 2006-12-18 US US12/158,121 patent/US7772875B2/en active Active
- 2006-12-18 DE DE602006015703T patent/DE602006015703D1/de active Active
- 2006-12-18 CN CNA2006800480534A patent/CN101341417A/zh active Pending
- 2006-12-18 JP JP2008546783A patent/JP2009521124A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE602006015703D1 (de) | 2010-09-02 |
WO2007072398A2 (en) | 2007-06-28 |
US20080272799A1 (en) | 2008-11-06 |
JP2009521124A (ja) | 2009-05-28 |
EP1977261A2 (de) | 2008-10-08 |
US7772875B2 (en) | 2010-08-10 |
WO2007072398A3 (en) | 2007-10-25 |
CN101341417A (zh) | 2009-01-07 |
EP1977261B1 (de) | 2010-07-21 |
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Legal Events
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---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |