ATE457503T1 - Neuronalnetzwerksbaustein - Google Patents

Neuronalnetzwerksbaustein

Info

Publication number
ATE457503T1
ATE457503T1 AT00968107T AT00968107T ATE457503T1 AT E457503 T1 ATE457503 T1 AT E457503T1 AT 00968107 T AT00968107 T AT 00968107T AT 00968107 T AT00968107 T AT 00968107T AT E457503 T1 ATE457503 T1 AT E457503T1
Authority
AT
Austria
Prior art keywords
building block
neuronal network
network building
processing element
digital memory
Prior art date
Application number
AT00968107T
Other languages
English (en)
Inventor
Stephen Byrun Furber
Original Assignee
Univ Manchester
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Manchester filed Critical Univ Manchester
Application granted granted Critical
Publication of ATE457503T1 publication Critical patent/ATE457503T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
AT00968107T 1999-10-15 2000-10-16 Neuronalnetzwerksbaustein ATE457503T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9924310.7A GB9924310D0 (en) 1999-10-15 1999-10-15 Neural network component
PCT/GB2000/003957 WO2001029766A2 (en) 1999-10-15 2000-10-16 Neural network component

Publications (1)

Publication Number Publication Date
ATE457503T1 true ATE457503T1 (de) 2010-02-15

Family

ID=10862720

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00968107T ATE457503T1 (de) 1999-10-15 2000-10-16 Neuronalnetzwerksbaustein

Country Status (9)

Country Link
US (1) US7457787B1 (de)
EP (1) EP1224619B1 (de)
JP (1) JP4931311B2 (de)
AT (1) ATE457503T1 (de)
AU (1) AU7806500A (de)
DE (1) DE60043824D1 (de)
ES (1) ES2338751T3 (de)
GB (1) GB9924310D0 (de)
WO (1) WO2001029766A2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8515885B2 (en) 2010-10-29 2013-08-20 International Business Machines Corporation Neuromorphic and synaptronic spiking neural network with synaptic weights learned using simulation
US8812414B2 (en) 2011-05-31 2014-08-19 International Business Machines Corporation Low-power event-driven neural computing architecture in neural networks
US8843425B2 (en) * 2011-07-29 2014-09-23 International Business Machines Corporation Hierarchical routing for two-way information flow and structural plasticity in neural networks
US8909576B2 (en) 2011-09-16 2014-12-09 International Business Machines Corporation Neuromorphic event-driven neural computing architecture in a scalable neural network
US8924322B2 (en) * 2012-06-15 2014-12-30 International Business Machines Corporation Multi-processor cortical simulations with reciprocal connections with shared weights
US8918351B2 (en) 2012-07-30 2014-12-23 International Business Machines Corporation Providing transposable access to a synapse array using column aggregation
US9218564B2 (en) 2012-07-30 2015-12-22 International Business Machines Corporation Providing transposable access to a synapse array using a recursive array layout
US9159020B2 (en) 2012-09-14 2015-10-13 International Business Machines Corporation Multiplexing physical neurons to optimize power and area
US8990130B2 (en) 2012-11-21 2015-03-24 International Business Machines Corporation Consolidating multiple neurosynaptic cores into one memory
US9558443B2 (en) 2013-08-02 2017-01-31 International Business Machines Corporation Dual deterministic and stochastic neurosynaptic core circuit
US9852006B2 (en) 2014-03-28 2017-12-26 International Business Machines Corporation Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits
US10410109B2 (en) 2014-08-25 2019-09-10 International Business Machines Corporation Peripheral device interconnections for neurosynaptic systems
US10832137B2 (en) 2018-01-30 2020-11-10 D5Ai Llc Merging multiple nodal networks
CN111602149B (zh) * 2018-01-30 2024-04-02 D5Ai有限责任公司 自组织偏序网络

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148385A (en) * 1987-02-04 1992-09-15 Texas Instruments Incorporated Serial systolic processor
JP2588195B2 (ja) * 1987-05-28 1997-03-05 株式会社東芝 パルス入力装置
JP3210319B2 (ja) 1990-03-01 2001-09-17 株式会社東芝 ニューロチップおよびそのチップを用いたニューロコンピュータ
DE4215179A1 (de) * 1991-05-08 1992-11-12 Caterpillar Inc Prozessor und verarbeitendes element zum gebrauch in einem neural- oder nervennetzwerk
US6894639B1 (en) * 1991-12-18 2005-05-17 Raytheon Company Generalized hebbian learning for principal component analysis and automatic target recognition, systems and method
US5278945A (en) * 1992-01-10 1994-01-11 American Neuralogical, Inc. Neural processor apparatus
US5404556A (en) * 1992-06-15 1995-04-04 California Institute Of Technology Apparatus for carrying out asynchronous communication among integrated circuits
US5920852A (en) * 1996-04-30 1999-07-06 Grannet Corporation Large memory storage and retrieval (LAMSTAR) network
IL133384A0 (en) * 1997-06-11 2001-04-30 Univ Southern California Dynamic synapse for signal processing in neural networks
US6516309B1 (en) * 1998-07-17 2003-02-04 Advanced Research & Technology Institute Method and apparatus for evolving a neural network

Also Published As

Publication number Publication date
WO2001029766A2 (en) 2001-04-26
JP4931311B2 (ja) 2012-05-16
DE60043824D1 (de) 2010-03-25
US7457787B1 (en) 2008-11-25
EP1224619B1 (de) 2010-02-10
JP2003512683A (ja) 2003-04-02
GB9924310D0 (en) 1999-12-15
EP1224619A2 (de) 2002-07-24
WO2001029766A3 (en) 2002-04-25
AU7806500A (en) 2001-04-30
ES2338751T3 (es) 2010-05-12

Similar Documents

Publication Publication Date Title
ATE457503T1 (de) Neuronalnetzwerksbaustein
DE612205T1 (de) Eingabe/Ausgabe-Einrichtung.
KR890010751A (ko) 뉴럴네트
WO1999009799A3 (de) Hörgerät
FR2693575B1 (fr) Carte à mémoire de masse avec fonction entrée/sortie.
DE3888703D1 (de) ECL-kompatible Eingangs-/Ausgangsschaltungen in CMOS-Technik.
SE9801738L (sv) Lågeffekträknare
RU99118678A (ru) Способ для инициализации моделирования поведения технической установки и система моделирования для технической установки
KR910021155A (ko) 비디오 신호 처리용 시스템
EP0104859A3 (de) Multiprozessor-Abbildungsspeicher
ATE523847T1 (de) Digitaler signalprozessor mit mehreren unabhängigen zugeordneten prozessoren
NO20032984D0 (no) Kontrollanordning basert på buss-teknologi
RU2001117944A (ru) Многопроцессорная информационно-управляющая система релейной защиты и автоматики
KR900010582A (ko) 데이타 처리기용 결합 회로망
RU2003125391A (ru) Автоматизированная система контроля
RU2037269C1 (ru) Преобразователь четырехразрядного кода грея в двоично-десятичный код
SU473181A1 (ru) Устройство дл сравнени двоичных чисел
SU997847A1 (ru) Узел управлени в сортирующих устройствах
RU2002109113A (ru) Робастная система управления
SU556500A1 (ru) Ячейка пам ти дл сдвигового регистра
RU97105958A (ru) Вычислитель ранговой статистики
KR890010690A (ko) 전 가산기를 이용한 승수회로
RU2003101493A (ru) Электронный ключ
RU96118306A (ru) Устройство для моделирования системы радиосвязи
JPS62169845U (de)

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties