ATE434807T1 - Vorrichtung und verfahren zur beschleunigung eines sonderzweckprozessors - Google Patents

Vorrichtung und verfahren zur beschleunigung eines sonderzweckprozessors

Info

Publication number
ATE434807T1
ATE434807T1 AT04257054T AT04257054T ATE434807T1 AT E434807 T1 ATE434807 T1 AT E434807T1 AT 04257054 T AT04257054 T AT 04257054T AT 04257054 T AT04257054 T AT 04257054T AT E434807 T1 ATE434807 T1 AT E434807T1
Authority
AT
Austria
Prior art keywords
special purpose
purpose processor
processor
accelerating
gpu
Prior art date
Application number
AT04257054T
Other languages
English (en)
Inventor
Jen-Hsun Huang
Michael Brian Cox
Ziyad S Hakura
John D Montrym
Brad W Simeral
Brian Keith Langendorf
Blanton Scott Kephart
Frank R Diard
Original Assignee
Nvidia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nvidia Corp filed Critical Nvidia Corp
Application granted granted Critical
Publication of ATE434807T1 publication Critical patent/ATE434807T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Image Generation (AREA)
  • Hardware Redundancy (AREA)
  • Image Processing (AREA)
  • Advance Control (AREA)
  • Control Of Stepping Motors (AREA)
AT04257054T 2003-12-11 2004-11-12 Vorrichtung und verfahren zur beschleunigung eines sonderzweckprozessors ATE434807T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/732,445 US7053901B2 (en) 2003-12-11 2003-12-11 System and method for accelerating a special purpose processor

Publications (1)

Publication Number Publication Date
ATE434807T1 true ATE434807T1 (de) 2009-07-15

Family

ID=34523048

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04257054T ATE434807T1 (de) 2003-12-11 2004-11-12 Vorrichtung und verfahren zur beschleunigung eines sonderzweckprozessors

Country Status (5)

Country Link
US (1) US7053901B2 (de)
EP (1) EP1542160B1 (de)
AT (1) ATE434807T1 (de)
DE (1) DE602004021667D1 (de)
TW (1) TWI298454B (de)

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US20080094403A1 (en) * 2003-11-19 2008-04-24 Reuven Bakalash Computing system capable of parallelizing the operation graphics processing units (GPUs) supported on a CPU/GPU fusion-architecture chip and one or more external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem
US20080079737A1 (en) * 2003-11-19 2008-04-03 Reuven Bakalash Multi-mode parallel graphics rendering and display system supporting real-time detection of mode control commands (MCCS) programmed within pre-profiled scenes of the graphics-based application
US8085273B2 (en) 2003-11-19 2011-12-27 Lucid Information Technology, Ltd Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US20090027383A1 (en) * 2003-11-19 2009-01-29 Lucid Information Technology, Ltd. Computing system parallelizing the operation of multiple graphics processing pipelines (GPPLs) and supporting depth-less based image recomposition
US8497865B2 (en) 2006-12-31 2013-07-30 Lucid Information Technology, Ltd. Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS
EP1687732A4 (de) * 2003-11-19 2008-11-19 Lucid Information Technology Ltd Verfahren und system für eine mehrfach-3d-graphikpipeline über einen pc-bus
US20070291040A1 (en) * 2005-01-25 2007-12-20 Reuven Bakalash Multi-mode parallel graphics rendering system supporting dynamic profiling of graphics-based applications and automatic control of parallel modes of operation
US7450120B1 (en) * 2003-12-19 2008-11-11 Nvidia Corporation Apparatus, system, and method for Z-culling
US8490101B1 (en) * 2004-11-29 2013-07-16 Oracle America, Inc. Thread scheduling in chip multithreading processors
JP2008538620A (ja) * 2005-01-25 2008-10-30 ルーシッド インフォメイション テクノロジー リミテッド モノリシック構成のシリコン・チップ上に多数のグラフィックス・コアを用いるグラフィック処理及び表示システム
US20090096798A1 (en) * 2005-01-25 2009-04-16 Reuven Bakalash Graphics Processing and Display System Employing Multiple Graphics Cores on a Silicon Chip of Monolithic Construction
US7839854B2 (en) * 2005-03-08 2010-11-23 Thomas Alexander System and method for a fast, programmable packet processing system
US20070005852A1 (en) * 2005-06-30 2007-01-04 International Business Machines Corporation Graphical verification tool for packet-based interconnect bus
JP4327175B2 (ja) * 2005-07-12 2009-09-09 株式会社ソニー・コンピュータエンタテインメント マルチグラフィックプロセッサシステム、グラフィックプロセッサおよび描画処理方法
US8570331B1 (en) 2006-08-24 2013-10-29 Nvidia Corporation System, method, and computer program product for policy-based routing of objects in a multi-graphics processor environment
US8207972B2 (en) * 2006-12-22 2012-06-26 Qualcomm Incorporated Quick pixel rendering processing
US8179394B1 (en) * 2007-12-13 2012-05-15 Nvidia Corporation Cull streams for fine-grained rendering predication
US8102393B1 (en) * 2007-12-13 2012-01-24 Nvidia Corporation Cull streams for fine-grained rendering predication
US9489767B1 (en) 2007-12-13 2016-11-08 Nvidia Corporation Cull streams for fine-grained rendering predication
US8330762B2 (en) 2007-12-19 2012-12-11 Advanced Micro Devices, Inc. Efficient video decoding migration for multiple graphics processor systems
US10157492B1 (en) 2008-10-02 2018-12-18 Nvidia Corporation System and method for transferring pre-computed Z-values between GPUS
US8395619B1 (en) * 2008-10-02 2013-03-12 Nvidia Corporation System and method for transferring pre-computed Z-values between GPUs
US8228337B1 (en) 2008-10-03 2012-07-24 Nvidia Corporation System and method for temporal load balancing across GPUs
US8427474B1 (en) * 2008-10-03 2013-04-23 Nvidia Corporation System and method for temporal load balancing across GPUs
TWI497396B (zh) * 2009-10-13 2015-08-21 Via Tech Inc 三維物件旋轉方法，與其對應的電腦系統和記錄媒體
US8941655B2 (en) 2011-09-07 2015-01-27 Qualcomm Incorporated Memory copy engine for graphics processing
TWI510056B (zh) * 2011-12-27 2015-11-21 Hon Hai Prec Ind Co Ltd 3d成像模組及3d成像方法
US9159156B2 (en) * 2012-05-14 2015-10-13 Nvidia Corporation Cull streams for fine-grained rendering predication
US10101982B2 (en) * 2013-01-31 2018-10-16 Htc Corporation Methods for application management in an electronic device supporting hardware acceleration
US11295506B2 (en) 2015-09-16 2022-04-05 Tmrw Foundation Ip S. À R.L. Chip with game engine and ray trace engine
TWM518034U (zh) 2015-11-09 2016-03-01 zhi-liang Chen 倒立椅
US11301951B2 (en) 2018-03-15 2022-04-12 The Calany Holding S. À R.L. Game engine and artificial intelligence engine on a chip
US11625884B2 (en) 2019-06-18 2023-04-11 The Calany Holding S. À R.L. Systems, methods and apparatus for implementing tracked data communications on a chip

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US6184908B1 (en) * 1998-04-27 2001-02-06 Ati Technologies, Inc. Method and apparatus for co-processing video graphics data
US6247113B1 (en) 1998-05-27 2001-06-12 Arm Limited Coprocessor opcode division by data type
US6097400A (en) * 1998-06-01 2000-08-01 Ati Technologies, Inc. Method and apparatus for anti-aliasing post rendering of an image
US6646639B1 (en) * 1998-07-22 2003-11-11 Nvidia Corporation Modified method and apparatus for improved occlusion culling in graphics systems
US6323860B1 (en) * 1999-03-17 2001-11-27 Nvidia Corporation Circuit and method for deferring the binding of render states to primitives in a graphics system
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Also Published As

Publication number Publication date
US7053901B2 (en) 2006-05-30
TWI298454B (en) 2008-07-01
EP1542160B1 (de) 2009-06-24
US20050128203A1 (en) 2005-06-16
DE602004021667D1 (de) 2009-08-06
TW200529041A (en) 2005-09-01
EP1542160A1 (de) 2005-06-15

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