ATE422120T1 - Verwaltung von anzapfstellen in einer digitalen verzögerungsleitung - Google Patents

Verwaltung von anzapfstellen in einer digitalen verzögerungsleitung

Info

Publication number
ATE422120T1
ATE422120T1 AT05825920T AT05825920T ATE422120T1 AT E422120 T1 ATE422120 T1 AT E422120T1 AT 05825920 T AT05825920 T AT 05825920T AT 05825920 T AT05825920 T AT 05825920T AT E422120 T1 ATE422120 T1 AT E422120T1
Authority
AT
Austria
Prior art keywords
rate clock
delay line
digital delay
chip
sample
Prior art date
Application number
AT05825920T
Other languages
English (en)
Inventor
Mark Wallis
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE422120T1 publication Critical patent/ATE422120T1/de

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/707Spread spectrum techniques using direct sequence modulation
    • H04B1/7097Interference-related aspects
    • H04B1/711Interference-related aspects the interference being multi-path interference
    • H04B1/7115Constructive combining of multi-path signals, i.e. RAKE receivers
AT05825920T 2004-12-03 2005-11-30 Verwaltung von anzapfstellen in einer digitalen verzögerungsleitung ATE422120T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04300844 2004-12-03

Publications (1)

Publication Number Publication Date
ATE422120T1 true ATE422120T1 (de) 2009-02-15

Family

ID=36565422

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05825920T ATE422120T1 (de) 2004-12-03 2005-11-30 Verwaltung von anzapfstellen in einer digitalen verzögerungsleitung

Country Status (7)

Country Link
US (1) US8238409B2 (de)
EP (1) EP1864412B1 (de)
JP (1) JP4904596B2 (de)
CN (1) CN101116255B (de)
AT (1) ATE422120T1 (de)
DE (1) DE602005012605D1 (de)
WO (1) WO2006059281A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080095141A1 (en) * 2006-09-21 2008-04-24 Broadcom Corporation Cluster Path Processor Multi-Mode Time Alignment Having Expanded Search Window
CN102386981B (zh) * 2010-08-31 2014-05-21 宏碁股份有限公司 适应性时脉控制方法及适应性时脉控制器
CN103888269B (zh) * 2014-03-04 2017-02-15 南京磐能电力科技股份有限公司 一种可编程网络延时器的实现方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US231703A (en) * 1880-08-31 Alfeed deedge
DE69835874T2 (de) 1998-07-13 2007-04-12 Hewlett-Packard Development Co., L.P., Houston Chipströmedekodierung
JP2000174661A (ja) * 1998-12-04 2000-06-23 Kokusai Electric Co Ltd 相関方法及びマッチドフィルタ及び携帯端末
US6639956B1 (en) * 1999-12-31 2003-10-28 Intel Corporation Data resynchronization circuit
EP1323234B1 (de) 2000-10-06 2011-12-07 Xilinx, Inc. Digitaler phasenschieber
JP3869674B2 (ja) * 2001-03-27 2007-01-17 株式会社日立国際電気 スペクトラム拡散通信用スライディングコリレータ
US7076678B2 (en) * 2002-02-11 2006-07-11 Micron Technology, Inc. Method and apparatus for data transfer
US7684471B2 (en) 2002-04-04 2010-03-23 Stmicroelectronics Asia Pacific Pte. Ltd. Rake-finger combiner with reduced resource requirement
EP1376886A1 (de) 2002-06-17 2004-01-02 Agilent Technologies, Inc. - a Delaware corporation - Entwurf der Verzögerungsleitung in einem Rake-Empfänger
JP4183683B2 (ja) * 2002-11-15 2008-11-19 テレコム・イタリア・エッセ・ピー・アー タイミングジッタの小さいアーリーレイト同期装置

Also Published As

Publication number Publication date
DE602005012605D1 (de) 2009-03-19
US8238409B2 (en) 2012-08-07
CN101116255A (zh) 2008-01-30
CN101116255B (zh) 2012-07-04
WO2006059281A3 (en) 2007-10-18
EP1864412A2 (de) 2007-12-12
EP1864412B1 (de) 2009-01-28
JP4904596B2 (ja) 2012-03-28
JP2008522529A (ja) 2008-06-26
WO2006059281A2 (en) 2006-06-08
US20100103996A1 (en) 2010-04-29

Similar Documents

Publication Publication Date Title
WO2005101164A3 (en) Delay line synchronizer apparatus and method
WO2002015502A3 (en) Adaptive linear equalisation for walsh-modulated
WO2006086168A3 (en) High data rate transmitter and receiver
DK1684265T3 (da) Fremgangsmåde til indlejring af et digitalt vandmærke i et anvendeligt signal
WO2008103658A3 (en) Transmission of prioritized information in the proximity of referenced signals
WO2007114944A3 (en) Phase control block for managing multiple clock domains in systems with frequency offsets
WO2008027066A3 (en) Clock and data recovery
WO2007120957A3 (en) Dynamic timing adjustment in a circuit device
EP1389860A3 (de) Frequenzablageschätzer
ATE524908T1 (de) Kommunikationsempfänger mit einer veränderlichen entzerrerlänge
WO2004082187A3 (en) System and method for compressing data in a communications environment
TW200633452A (en) Timing recovery methods and apparatuses
ATE288599T1 (de) Methode und system zur automatischen verzögerungserkennung und empfängeranpassung für eine synchrone busschnittstelle
EP1009125A3 (de) Bitsynchronisierungsschaltung mit Überabtastung der empfangenen Daten zur Bestimmung deren Inhalts
SE0102849D0 (sv) Methods and arrangements in a telecommunicaton system
WO2008027792A3 (en) Power line communication device and method with frequency shifted modem
ATE422120T1 (de) Verwaltung von anzapfstellen in einer digitalen verzögerungsleitung
NO20060285L (no) Mottager som har digital tidsstyringsgjenvinningsfunksjon
DE602004024331D1 (de) Programmtaktreferenzsynchronisation in multimedia-netzwerken
TW200711302A (en) A dynamic input setup/hold time improvement architecture
TW200638206A (en) Multi-channel receiver, digital edge tuning circuit and method thereof
ATE438972T1 (de) Zeichengabe mit mehreren taktleitungen
DE602005015335D1 (de) Abtastwertbeschaffungs-timing-justierung
ATE317567T1 (de) Digitales bussystem
DE50105475D1 (de) Demodulator für cpfsk-modulierte signale unter verwendung einer linearen näherung des cpfsk-signals

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties