ATE408979T1 - Leiterplatte mit identifizierbaren informationen und herstellungsverfahren - Google Patents

Leiterplatte mit identifizierbaren informationen und herstellungsverfahren

Info

Publication number
ATE408979T1
ATE408979T1 AT04018155T AT04018155T ATE408979T1 AT E408979 T1 ATE408979 T1 AT E408979T1 AT 04018155 T AT04018155 T AT 04018155T AT 04018155 T AT04018155 T AT 04018155T AT E408979 T1 ATE408979 T1 AT E408979T1
Authority
AT
Austria
Prior art keywords
circuit board
identifiable information
circuit
manufacturing process
insulating layer
Prior art date
Application number
AT04018155T
Other languages
English (en)
Inventor
Shih-Ping Hsu
Shang-Wei Chen
Suo-Hsia Tang
Chao-Wen Shih
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Application granted granted Critical
Publication of ATE408979T1 publication Critical patent/ATE408979T1/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09927—Machine readable code, e.g. bar code
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09936—Marks, inscriptions, etc. for information
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Making Paper Articles (AREA)
AT04018155T 2004-07-30 2004-07-30 Leiterplatte mit identifizierbaren informationen und herstellungsverfahren ATE408979T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04018155A EP1622431B1 (de) 2004-07-30 2004-07-30 Leiterplatte mit identifizierbaren Informationen und Herstellungsverfahren

Publications (1)

Publication Number Publication Date
ATE408979T1 true ATE408979T1 (de) 2008-10-15

Family

ID=34926010

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04018155T ATE408979T1 (de) 2004-07-30 2004-07-30 Leiterplatte mit identifizierbaren informationen und herstellungsverfahren

Country Status (3)

Country Link
EP (1) EP1622431B1 (de)
AT (1) ATE408979T1 (de)
DE (1) DE602004016648D1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6208054B2 (ja) * 2014-03-10 2017-10-04 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
CN110321749B (zh) 2018-03-28 2022-05-13 奥特斯(中国)有限公司 用于部件承载件的双重编码可追踪系统
CN108811303A (zh) * 2018-06-13 2018-11-13 广州兴森快捷电路科技有限公司 封装基板及其加工方法
EP3723459A1 (de) 2019-04-10 2020-10-14 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Komponententräger mit hoher passiver intermodulationsleistung (pim)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3027410A1 (de) * 1980-07-19 1982-02-18 Schering Ag, 1000 Berlin Und 4619 Bergkamen Verfahren zur eingabe von informationen an galvanisieranlagen, sowie zugehoerige ware und vorrichtung
US4642160A (en) * 1985-08-12 1987-02-10 Interconnect Technology Inc. Multilayer circuit board manufacturing
JP2000340950A (ja) * 1999-05-31 2000-12-08 Matsushita Electric Ind Co Ltd 多層回路基板における積層合致精度検査マーク構造
JP2002237669A (ja) * 2001-02-09 2002-08-23 Yamaichi Electronics Co Ltd Ｋｇｄ用サブストレートへの認識マークの形成方法
EP1280204A3 (de) * 2001-06-27 2004-09-01 Shinko Electric Industries Co. Ltd. Schaltungssubstrat mit Positionierungsmarke

Also Published As

Publication number Publication date
EP1622431B1 (de) 2008-09-17
DE602004016648D1 (de) 2008-10-30
EP1622431A1 (de) 2006-02-01

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties
REN Ceased due to non-payment of the annual fee