ATE404913T1 - Anordnung und verfahren zum quadrieren von langen ganzzahlen - Google Patents

Anordnung und verfahren zum quadrieren von langen ganzzahlen

Info

Publication number
ATE404913T1
ATE404913T1 AT02719024T AT02719024T ATE404913T1 AT E404913 T1 ATE404913 T1 AT E404913T1 AT 02719024 T AT02719024 T AT 02719024T AT 02719024 T AT02719024 T AT 02719024T AT E404913 T1 ATE404913 T1 AT E404913T1
Authority
AT
Austria
Prior art keywords
recursive
indexing parameter
logic circuit
logic circuits
value
Prior art date
Application number
AT02719024T
Other languages
English (en)
Inventor
Paul W Dent
Ben Smeets
Iii William J Croughwell
Original Assignee
Ericsson Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Inc filed Critical Ericsson Inc
Application granted granted Critical
Publication of ATE404913T1 publication Critical patent/ATE404913T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/552—Powers or roots, e.g. Pythagorean sums
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/722—Modular multiplication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H04L9/3006—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters
    • H04L9/302—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters involving the integer factorization problem, e.g. RSA or quadratic sieve [QS] schemes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/552—Indexing scheme relating to groups G06F7/552 - G06F7/5525
    • G06F2207/5523—Calculates a power, e.g. the square, of a number or a function, e.g. polynomials
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G06F2207/7223—Randomisation as countermeasure against side channel attacks
    • G06F2207/7252—Randomisation as countermeasure against side channel attacks of operation order, e.g. starting to treat the exponent at a random place, or in a randomly chosen direction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/723—Modular exponentiation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/122—Hardware reduction or efficient architectures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Complex Calculations (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Devices For Executing Special Programs (AREA)
  • Dental Preparations (AREA)
  • Escalators And Moving Walkways (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Paper (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
AT02719024T 2001-03-06 2002-02-20 Anordnung und verfahren zum quadrieren von langen ganzzahlen ATE404913T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/800,145 US7113593B2 (en) 2001-03-06 2001-03-06 Recursive cryptoaccelerator and recursive VHDL design of logic circuits

Publications (1)

Publication Number Publication Date
ATE404913T1 true ATE404913T1 (de) 2008-08-15

Family

ID=25177603

Family Applications (2)

Application Number Title Priority Date Filing Date
AT02719024T ATE404913T1 (de) 2001-03-06 2002-02-20 Anordnung und verfahren zum quadrieren von langen ganzzahlen
AT07100110T ATE419578T1 (de) 2001-03-06 2002-02-20 Schaltkreis und verfahren zur vervielfältigung langer ganzzahliger werte

Family Applications After (1)

Application Number Title Priority Date Filing Date
AT07100110T ATE419578T1 (de) 2001-03-06 2002-02-20 Schaltkreis und verfahren zur vervielfältigung langer ganzzahliger werte

Country Status (5)

Country Link
US (1) US7113593B2 (de)
EP (3) EP1366596B1 (de)
AT (2) ATE404913T1 (de)
DE (2) DE60228207D1 (de)
WO (1) WO2002071687A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8781110B2 (en) * 2007-06-30 2014-07-15 Intel Corporation Unified system architecture for elliptic-curve cryptography
US8572406B2 (en) * 2010-03-31 2013-10-29 Inside Contactless Integrated circuit protected against horizontal side channel analysis
EP2365659B1 (de) 2010-03-01 2017-04-12 Inside Secure Testverfahren des Widerstands eines integrierten Schaltkreises gegenüber einem Seitenkanalangriff
FR2956933A1 (fr) * 2010-03-01 2011-09-02 Inside Contactless Circuit integre protege contre une analyse par canal auxiliaire horizontale
CN103765493B (zh) * 2011-09-06 2017-10-24 英特尔公司 数字平方计算机实现的方法和设备
US9355068B2 (en) 2012-06-29 2016-05-31 Intel Corporation Vector multiplication with operand base system conversion and re-conversion
US10095516B2 (en) 2012-06-29 2018-10-09 Intel Corporation Vector multiplication with accumulation in large register space
EP4095826A4 (de) * 2020-01-20 2023-10-25 Nippon Telegraph And Telephone Corporation Sichere rechnervorrichtung, sicheres berechnungsverfahren und programm
US11636176B2 (en) * 2020-09-25 2023-04-25 Apple Inc. Interpolation method and apparatus for arithmetic functions

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4313174A (en) * 1980-03-17 1982-01-26 Rockwell International Corporation ROM-Based parallel digital arithmetic device
US5765207A (en) * 1993-06-22 1998-06-09 International Business Machines Corporation Recursive hardware state machine
US5963454A (en) * 1996-09-25 1999-10-05 Vlsi Technology, Inc. Method and apparatus for efficiently implementing complex function blocks in integrated circuit designs
US5828590A (en) * 1996-11-27 1998-10-27 United Microelectronics Corp. Multiplier based on a variable radix multiplier coding
FR2758195B1 (fr) * 1997-01-09 1999-02-26 Sgs Thomson Microelectronics Coprocesseur d'arithmetique modulaire comprenant deux circuits de multiplication operant en parallele
US6289498B1 (en) * 1998-02-20 2001-09-11 Lsi Logic Corporation VDHL/Verilog expertise and gate synthesis automation system
US6044390A (en) * 1998-04-16 2000-03-28 V L S I Technology, Inc. Recursive lookahead-based 2n -bit serial multipliers over Galois Field GF (2m)

Also Published As

Publication number Publication date
EP1818811A3 (de) 2008-01-02
DE60230690D1 (de) 2009-02-12
EP1818811A2 (de) 2007-08-15
WO2002071687A1 (en) 2002-09-12
EP1818810A3 (de) 2007-12-12
ATE419578T1 (de) 2009-01-15
EP1366596B1 (de) 2008-08-13
EP1366596A1 (de) 2003-12-03
DE60228207D1 (de) 2008-09-25
EP1818810A2 (de) 2007-08-15
US7113593B2 (en) 2006-09-26
EP1818810B1 (de) 2008-12-31
EP1366596A4 (de) 2006-05-03
US20030016822A1 (en) 2003-01-23

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