JPS6418240A - Wiring system for integrated circuit - Google Patents

Wiring system for integrated circuit

Info

Publication number
JPS6418240A
JPS6418240A JP17537287A JP17537287A JPS6418240A JP S6418240 A JPS6418240 A JP S6418240A JP 17537287 A JP17537287 A JP 17537287A JP 17537287 A JP17537287 A JP 17537287A JP S6418240 A JPS6418240 A JP S6418240A
Authority
JP
Japan
Prior art keywords
integrated circuit
wiring pattern
cell
whose
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17537287A
Other languages
Japanese (ja)
Inventor
Masaki Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17537287A priority Critical patent/JPS6418240A/en
Publication of JPS6418240A publication Critical patent/JPS6418240A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To generate an integrated circuit having various regular structures equally to a manual designing operation, at high speed and at a high density by a method wherein a wiring system adapted to a characteristic of individual integrated circuits is applied. CONSTITUTION:A part which can be designed by a repeated pattern is made by macrocells 2 in an integrated circuit 1 having regular structures. These macrocells 2 are connected by the following according to the degree of freedom of a wiring pattern: a fixed pattern cell 5 where the wiring pattern has been written; a parameterbased cell 7 whose wiring pattern is changed according to a parameter; an automatic router cell 8 whose wiring pattern is decided by an automatic router whose wiring region can be reduced to a minimum. By this setup, it is possible to generate the integrated circuit having various kinds of regular structures whose performance is equal to that by a manual designing operation in a short time and without an error.
JP17537287A 1987-07-13 1987-07-13 Wiring system for integrated circuit Pending JPS6418240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17537287A JPS6418240A (en) 1987-07-13 1987-07-13 Wiring system for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17537287A JPS6418240A (en) 1987-07-13 1987-07-13 Wiring system for integrated circuit

Publications (1)

Publication Number Publication Date
JPS6418240A true JPS6418240A (en) 1989-01-23

Family

ID=15994945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17537287A Pending JPS6418240A (en) 1987-07-13 1987-07-13 Wiring system for integrated circuit

Country Status (1)

Country Link
JP (1) JPS6418240A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5141477A (en) * 1991-03-18 1992-08-25 Nissan Motor Co., Ltd. Planetary gear drive with intermeshing planet pinions in multistage automatic transmission
JP2010529684A (en) * 2007-06-07 2010-08-26 ケーエルエー−テンカー・コーポレーション Computer-implemented method, carrier medium, and system for detecting defects on wafers based on multi-core structures

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5141477A (en) * 1991-03-18 1992-08-25 Nissan Motor Co., Ltd. Planetary gear drive with intermeshing planet pinions in multistage automatic transmission
JP2010529684A (en) * 2007-06-07 2010-08-26 ケーエルエー−テンカー・コーポレーション Computer-implemented method, carrier medium, and system for detecting defects on wafers based on multi-core structures

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