ATE401606T1 - Halbleiterbauelement mit mehreren speicherstrukturen - Google Patents

Halbleiterbauelement mit mehreren speicherstrukturen

Info

Publication number
ATE401606T1
ATE401606T1 AT04784950T AT04784950T ATE401606T1 AT E401606 T1 ATE401606 T1 AT E401606T1 AT 04784950 T AT04784950 T AT 04784950T AT 04784950 T AT04784950 T AT 04784950T AT E401606 T1 ATE401606 T1 AT E401606T1
Authority
AT
Austria
Prior art keywords
local memory
memory structure
semiconductor component
memory structures
multiple memory
Prior art date
Application number
AT04784950T
Other languages
English (en)
Inventor
Kenneth Goodnow
Francis Kampf
Jason Norman
Sebastian Ventrone
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE401606T1 publication Critical patent/ATE401606T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multi Processors (AREA)
  • Semiconductor Memories (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT04784950T 2003-09-25 2004-09-24 Halbleiterbauelement mit mehreren speicherstrukturen ATE401606T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/605,366 US7139881B2 (en) 2003-09-25 2003-09-25 Semiconductor device comprising a plurality of memory structures

Publications (1)

Publication Number Publication Date
ATE401606T1 true ATE401606T1 (de) 2008-08-15

Family

ID=34375640

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04784950T ATE401606T1 (de) 2003-09-25 2004-09-24 Halbleiterbauelement mit mehreren speicherstrukturen

Country Status (8)

Country Link
US (1) US7139881B2 (de)
EP (1) EP1665344B1 (de)
JP (1) JP4709761B2 (de)
KR (1) KR100834313B1 (de)
CN (1) CN100555242C (de)
AT (1) ATE401606T1 (de)
DE (1) DE602004015125D1 (de)
WO (1) WO2005031804A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7139881B2 (en) * 2003-09-25 2006-11-21 International Business Machines Corporation Semiconductor device comprising a plurality of memory structures
JP2007034943A (ja) * 2005-07-29 2007-02-08 Sony Corp 共有メモリ装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS547252A (en) * 1977-06-20 1979-01-19 Hitachi Ltd Program control system
CN85104907B (zh) * 1985-06-25 1987-10-14 株式会社日立制作所 分级多处理器系统及其控制方法
US5293491A (en) * 1990-12-28 1994-03-08 International Business Machines Corp. Data processing system and memory controller for lock semaphore operations
GB2283596B (en) * 1993-11-01 1998-07-01 Ericsson Ge Mobile Communicat Multiprocessor data memory sharing
US5940870A (en) * 1996-05-21 1999-08-17 Industrial Technology Research Institute Address translation for shared-memory multiprocessor clustering
JPH10134008A (ja) * 1996-11-05 1998-05-22 Mitsubishi Electric Corp 半導体装置およびコンピュータシステム
US5950228A (en) * 1997-02-03 1999-09-07 Digital Equipment Corporation Variable-grained memory sharing for clusters of symmetric multi-processors using private and shared state tables
FR2770665B1 (fr) * 1997-11-06 2002-12-20 Alsthom Cge Alkatel Dispositif d'echange entre unites de traitement d'informations a processeurs interconnectes par un bus commun
JP3976432B2 (ja) * 1998-12-09 2007-09-19 エヌイーシーコンピュータテクノ株式会社 データ処理装置およびデータ処理方法
JP2000276399A (ja) * 1999-03-24 2000-10-06 Nec Data Terminal Ltd アドレス制御方式
US6449699B2 (en) * 1999-03-29 2002-09-10 International Business Machines Corporation Apparatus and method for partitioned memory protection in cache coherent symmetric multiprocessor systems
US6457100B1 (en) * 1999-09-15 2002-09-24 International Business Machines Corporation Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls
JP2001338492A (ja) * 2000-05-26 2001-12-07 Matsushita Electric Ind Co Ltd 半導体装置と制御方法
US6684297B2 (en) * 2001-04-11 2004-01-27 Sun Microsystems, Inc. Reverse directory for facilitating accesses involving a lower-level cache
TWI230897B (en) * 2001-04-20 2005-04-11 Ibm Method for sharing a translation lookaside buffer between CPUs
DE10128475A1 (de) * 2001-06-12 2003-01-02 Siemens Ag Mehrprozessorsystem mit geteiltem Arbeitsspeicher
US6976131B2 (en) * 2002-08-23 2005-12-13 Intel Corporation Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
US7139881B2 (en) * 2003-09-25 2006-11-21 International Business Machines Corporation Semiconductor device comprising a plurality of memory structures

Also Published As

Publication number Publication date
JP2007507042A (ja) 2007-03-22
WO2005031804A2 (en) 2005-04-07
CN1856773A (zh) 2006-11-01
US20050071575A1 (en) 2005-03-31
KR20060088879A (ko) 2006-08-07
DE602004015125D1 (de) 2008-08-28
WO2005031804A3 (en) 2006-07-20
US7139881B2 (en) 2006-11-21
JP4709761B2 (ja) 2011-06-22
EP1665344A2 (de) 2006-06-07
KR100834313B1 (ko) 2008-06-02
EP1665344B1 (de) 2008-07-16
EP1665344A4 (de) 2007-07-18
CN100555242C (zh) 2009-10-28

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties