ATE393431T1 - Datenkommunikationsmodul zur bereitstellung von fehlertoleranz und vergrösserter stabilität - Google Patents

Datenkommunikationsmodul zur bereitstellung von fehlertoleranz und vergrösserter stabilität

Info

Publication number
ATE393431T1
ATE393431T1 AT05703030T AT05703030T ATE393431T1 AT E393431 T1 ATE393431 T1 AT E393431T1 AT 05703030 T AT05703030 T AT 05703030T AT 05703030 T AT05703030 T AT 05703030T AT E393431 T1 ATE393431 T1 AT E393431T1
Authority
AT
Austria
Prior art keywords
data bits
module
communication module
data communication
fault tolerance
Prior art date
Application number
AT05703030T
Other languages
English (en)
Inventor
Andre Nieuwland
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE393431T1 publication Critical patent/ATE393431T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Bus Control (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Communication Control (AREA)
AT05703030T 2004-03-03 2005-02-23 Datenkommunikationsmodul zur bereitstellung von fehlertoleranz und vergrösserter stabilität ATE393431T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04100853 2004-03-03

Publications (1)

Publication Number Publication Date
ATE393431T1 true ATE393431T1 (de) 2008-05-15

Family

ID=34928886

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05703030T ATE393431T1 (de) 2004-03-03 2005-02-23 Datenkommunikationsmodul zur bereitstellung von fehlertoleranz und vergrösserter stabilität

Country Status (9)

Country Link
US (1) US7849390B2 (de)
EP (1) EP1725941B1 (de)
JP (1) JP4649472B2 (de)
KR (1) KR20070006764A (de)
CN (1) CN100485646C (de)
AT (1) ATE393431T1 (de)
DE (1) DE602005006248T2 (de)
TW (1) TW200604816A (de)
WO (1) WO2005088467A1 (de)

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WO2006115819A1 (en) * 2005-04-21 2006-11-02 Iota Technology, Inc. Electronic differential buses utilizing the null state for data transfer
KR100845141B1 (ko) * 2007-01-17 2008-07-10 삼성전자주식회사 싱글 레이트 인터페이스 장치, 듀얼 레이트 인터페이스장치 및 듀얼 레이트 인터페이싱 방법
US7522073B1 (en) * 2007-11-30 2009-04-21 Qimonda North America Corp. Self-adapted bus inversion
WO2009108562A2 (en) 2008-02-25 2009-09-03 Rambus Inc. Code-assisted error-detection technique
TW201015874A (en) * 2008-10-14 2010-04-16 Univ Nat Changhua Education Encoding/decoding method of Berger invert codes, and its encoder and inspector circuit
US9087025B2 (en) 2009-02-05 2015-07-21 Micron Technology, Inc. Data encoding using spare channels in a memory system
JP2011159119A (ja) * 2010-02-01 2011-08-18 Fujitsu Ltd 情報処理装置、情報送信方法および情報受信方法
CN101788967B (zh) * 2010-03-09 2012-02-08 西安电子科技大学 抗串扰片上总线编解码方法及其编解码装置
CN101834704B (zh) * 2010-03-09 2013-01-23 西安电子科技大学 高性能抗串扰时空总线编解码方法及其编解码装置
CN101848059B (zh) * 2010-04-09 2013-08-14 西安电子科技大学 抑制总线串扰的自适应时间编解码装置及其编解码方法
DE102010031030B3 (de) * 2010-07-07 2011-11-17 Robert Bosch Gmbh Datenschnittstelle mit eigensicherer, integrierter Fehlererkennung
US8405529B2 (en) * 2011-03-11 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Using bus inversion to reduce simultaneous signal switching
JP5974700B2 (ja) * 2012-07-19 2016-08-23 富士通株式会社 伝送装置及びデータ転送方法
CN103731130B (zh) * 2013-12-27 2017-01-04 华为技术有限公司 通用的容错纠错电路及其应用的译码器和三模冗余电路
CN104808966B (zh) * 2014-01-29 2019-03-12 马维尔以色列(M.I.S.L.)有限公司 有效编码的方法和装置
US9979416B2 (en) 2014-12-10 2018-05-22 Rambus Inc. Memory controller and method of data bus inversion using an error detection correction code
CN111198838B (zh) * 2019-12-30 2020-10-20 中国人民解放军军事科学院国防科技创新研究院 一种双轨信号异步传输链路系统

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Publication number Priority date Publication date Assignee Title
US3889072A (en) * 1973-10-19 1975-06-10 Itt Bi-directional amplification apparatus
US4667337A (en) * 1985-08-28 1987-05-19 Westinghouse Electric Corp. Integrated circuit having outputs configured for reduced state changes
JPS62140155A (ja) 1985-12-16 1987-06-23 Nec Corp 装置のデ−タバス自動切替回路
JPH05334206A (ja) * 1992-05-29 1993-12-17 Toshiba Corp インターフェース制御装置
US5287527A (en) 1992-12-28 1994-02-15 International Business Machines Corporation Logical signal output drivers for integrated circuit interconnection
US5748902A (en) * 1996-07-19 1998-05-05 Compaq Computer Corporation Polarity switched data bus for reduced electromagnetic interference
US6046943A (en) * 1998-03-10 2000-04-04 Texas Instuments Incorporated Synchronous semiconductor device output circuit with reduced data switching
US6647245B1 (en) * 1999-05-28 2003-11-11 Glen V Rosenbaum Subsidiary communication authorization (SCA) radio turner
US6671212B2 (en) * 2002-02-08 2003-12-30 Ati Technologies Inc. Method and apparatus for data inversion in memory device

Also Published As

Publication number Publication date
US20080288844A1 (en) 2008-11-20
DE602005006248D1 (de) 2008-06-05
WO2005088467A1 (en) 2005-09-22
CN1926528A (zh) 2007-03-07
CN100485646C (zh) 2009-05-06
EP1725941B1 (de) 2008-04-23
KR20070006764A (ko) 2007-01-11
TW200604816A (en) 2006-02-01
DE602005006248T2 (de) 2009-06-25
JP4649472B2 (ja) 2011-03-09
US7849390B2 (en) 2010-12-07
JP2007526574A (ja) 2007-09-13
EP1725941A1 (de) 2006-11-29

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