ATE377767T1 - Verfahren und system zum simulieren eines modularen testsystems - Google Patents
Verfahren und system zum simulieren eines modularen testsystemsInfo
- Publication number
- ATE377767T1 ATE377767T1 AT05743583T AT05743583T ATE377767T1 AT E377767 T1 ATE377767 T1 AT E377767T1 AT 05743583 T AT05743583 T AT 05743583T AT 05743583 T AT05743583 T AT 05743583T AT E377767 T1 ATE377767 T1 AT E377767T1
- Authority
- AT
- Austria
- Prior art keywords
- simulating
- modular test
- test system
- simulation framework
- model
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US57357704P | 2004-05-22 | 2004-05-22 | |
US10/917,711 US7210087B2 (en) | 2004-05-22 | 2004-08-13 | Method and system for simulating a modular test system |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE377767T1 true ATE377767T1 (de) | 2007-11-15 |
Family
ID=34968284
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT05743583T ATE377767T1 (de) | 2004-05-22 | 2005-05-23 | Verfahren und system zum simulieren eines modularen testsystems |
Country Status (8)
Country | Link |
---|---|
US (1) | US7210087B2 (de) |
EP (1) | EP1756605B1 (de) |
JP (1) | JP3911007B1 (de) |
KR (1) | KR20070020247A (de) |
AT (1) | ATE377767T1 (de) |
DE (1) | DE602005003225T2 (de) |
TW (1) | TWI352211B (de) |
WO (1) | WO2005114237A1 (de) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040225459A1 (en) * | 2003-02-14 | 2004-11-11 | Advantest Corporation | Method and structure to develop a test program for semiconductor integrated circuits |
US7665067B2 (en) * | 2003-09-15 | 2010-02-16 | Cadence Design (Israel) Ii Ltd. | Method and system for automatically creating tests |
US20060026584A1 (en) * | 2004-07-27 | 2006-02-02 | Muratori Richard D | Explicit linking of dynamic link libraries |
US8171455B2 (en) * | 2004-08-13 | 2012-05-01 | Agilent Technologies, Inc. | Test sequencer and method for management and execution of sequence items |
US8082541B2 (en) * | 2004-12-09 | 2011-12-20 | Advantest Corporation | Method and system for performing installation and configuration management of tester instrument modules |
US7543200B2 (en) * | 2005-02-17 | 2009-06-02 | Advantest Corporation | Method and system for scheduling tests in a parallel test system |
US8214800B2 (en) * | 2005-03-02 | 2012-07-03 | Advantest Corporation | Compact representation of vendor hardware module revisions in an open architecture test system |
JP2006275986A (ja) * | 2005-03-30 | 2006-10-12 | Advantest Corp | 診断プログラム、切替プログラム、試験装置、および診断方法 |
US20070150254A1 (en) * | 2005-12-23 | 2007-06-28 | Choi Cathy Y | Simulation engine for a performance validation system |
US7869986B2 (en) * | 2006-07-10 | 2011-01-11 | Blancha Barry E | System and method for performing processing in a testing system |
WO2008014827A1 (en) | 2006-08-04 | 2008-02-07 | Verigy (Singapore) Pte. Ltd. | Test module with blocks of universal and specific resources |
US7809520B2 (en) * | 2007-11-05 | 2010-10-05 | Advantest Corporation | Test equipment, method for loading test plan and program product |
US20090119542A1 (en) * | 2007-11-05 | 2009-05-07 | Advantest Corporation | System, method, and program product for simulating test equipment |
US20090319247A1 (en) * | 2008-06-18 | 2009-12-24 | Eads Na Defense Security And Systems Solutions Inc | Systems and Methods for A Simulated Network Environment and Operation Thereof |
US8615373B2 (en) | 2011-01-06 | 2013-12-24 | International Business Machines Corporation | Voltage driver for a voltage-driven intelligent characterization bench for semiconductor |
US9043179B2 (en) | 2011-01-06 | 2015-05-26 | International Business Machines Corporation | Voltage-driven intelligent characterization bench for semiconductor |
US8839057B2 (en) * | 2011-02-03 | 2014-09-16 | Arm Limited | Integrated circuit and method for testing memory on the integrated circuit |
US10776233B2 (en) * | 2011-10-28 | 2020-09-15 | Teradyne, Inc. | Programmable test instrument |
US9759772B2 (en) | 2011-10-28 | 2017-09-12 | Teradyne, Inc. | Programmable test instrument |
US9470759B2 (en) | 2011-10-28 | 2016-10-18 | Teradyne, Inc. | Test instrument having a configurable interface |
JP5841458B2 (ja) * | 2012-03-01 | 2016-01-13 | 株式会社アドバンテスト | 試験装置および試験モジュール |
TWI456216B (zh) * | 2012-07-19 | 2014-10-11 | Novatek Microelectronics Corp | 積體電路及其測試系統 |
DE102013006012A1 (de) * | 2013-04-09 | 2014-10-09 | Airbus Defence and Space GmbH | Mehrbenutzerfähige Testumgebung für eine Mehrzahl von Testobjekten |
DE102013006011A1 (de) * | 2013-04-09 | 2014-10-09 | Airbus Defence and Space GmbH | Modulare Testumgebung für eine Mehrzahl von Testobjekten |
CN107305515A (zh) * | 2016-04-25 | 2017-10-31 | Emc公司 | 计算机实现方法、计算机程序产品以及计算系统 |
US10467366B2 (en) | 2016-10-14 | 2019-11-05 | Oracle International Corporation | Methods and systems for simulating high-speed link designs |
US10592370B2 (en) * | 2017-04-28 | 2020-03-17 | Advantest Corporation | User control of automated test features with software application programming interface (API) |
KR102583174B1 (ko) | 2018-06-12 | 2023-09-26 | 삼성전자주식회사 | 테스트 인터페이스 보드, 이를 포함하는 테스트 시스템 및 이의 동작 방법 |
WO2019238186A1 (en) * | 2018-06-13 | 2019-12-19 | Beumer Group A/S | Method for design and test of logistics and material handling systems |
WO2020105130A1 (ja) | 2018-11-20 | 2020-05-28 | 三菱電機株式会社 | 通信システム、リスト参照局、リスト配信局、通信方法、および通信プログラム |
US11302412B2 (en) * | 2019-06-03 | 2022-04-12 | Advantest Corporation | Systems and methods for simulated device testing using a memory-based communication protocol |
US11636019B2 (en) * | 2019-07-11 | 2023-04-25 | Walmart Apollo, Llc | Systems and methods for dynamically simulating load to an application under test |
CN110781103B (zh) * | 2019-11-05 | 2022-02-15 | 中电科思仪科技股份有限公司 | 一种pxi总线开关模块控制系统及方法 |
CN111400872B (zh) * | 2020-02-27 | 2023-11-17 | 中国商用飞机有限责任公司北京民用飞机技术研究中心 | 一种基于模型的航电系统虚拟集成测试方法及系统 |
CN116359716B (zh) * | 2023-05-31 | 2023-08-04 | 深圳市华测半导体设备有限公司 | 一种ic测试机动态分配测试资源的方法、系统及介质 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0143623A3 (de) | 1983-11-25 | 1987-09-23 | Mars Incorporated | Automatisches Prüfgerät |
JPH03130839A (ja) * | 1989-10-17 | 1991-06-04 | Chubu Nippon Denki Software Kk | オンラインシミュレーション方式 |
US5488573A (en) * | 1993-09-02 | 1996-01-30 | Matsushita Electric Industrial Co., Ltd. | Method for generating test programs |
US5892949A (en) * | 1996-08-30 | 1999-04-06 | Schlumberger Technologies, Inc. | ATE test programming architecture |
US6182258B1 (en) * | 1997-06-03 | 2001-01-30 | Verisity Ltd. | Method and apparatus for test generation during circuit design |
US6028439A (en) * | 1997-10-31 | 2000-02-22 | Credence Systems Corporation | Modular integrated circuit tester with distributed synchronization and control |
US6195774B1 (en) * | 1998-08-13 | 2001-02-27 | Xilinx, Inc. | Boundary-scan method using object-oriented programming language |
US6601018B1 (en) * | 1999-02-04 | 2003-07-29 | International Business Machines Corporation | Automatic test framework system and method in software component testing |
US6427223B1 (en) * | 1999-04-30 | 2002-07-30 | Synopsys, Inc. | Method and apparatus for adaptive verification of circuit designs |
US6678643B1 (en) | 1999-06-28 | 2004-01-13 | Advantest Corp. | Event based semiconductor test system |
US6405364B1 (en) * | 1999-08-31 | 2002-06-11 | Accenture Llp | Building techniques in a development architecture framework |
US6779140B2 (en) * | 2001-06-29 | 2004-08-17 | Agilent Technologies, Inc. | Algorithmically programmable memory tester with test sites operating in a slave mode |
DE10392497T5 (de) | 2002-04-11 | 2005-02-17 | Advantest Corp. | Herstellungsverfahren und Herstellungsvorrichtung zum Vermeiden eines Prototypen-Aufschubs bei der ASIC/SOC-Herstellung |
US7460988B2 (en) * | 2003-03-31 | 2008-12-02 | Advantest Corporation | Test emulator, test module emulator, and record medium storing program therein |
US7197417B2 (en) * | 2003-02-14 | 2007-03-27 | Advantest America R&D Center, Inc. | Method and structure to develop a test program for semiconductor integrated circuits |
US7184917B2 (en) * | 2003-02-14 | 2007-02-27 | Advantest America R&D Center, Inc. | Method and system for controlling interchangeable components in a modular test system |
TWI344595B (en) | 2003-02-14 | 2011-07-01 | Advantest Corp | Method and structure to develop a test program for semiconductor integrated circuits |
US20040225459A1 (en) * | 2003-02-14 | 2004-11-11 | Advantest Corporation | Method and structure to develop a test program for semiconductor integrated circuits |
-
2004
- 2004-08-13 US US10/917,711 patent/US7210087B2/en not_active Expired - Fee Related
-
2005
- 2005-05-18 TW TW094116148A patent/TWI352211B/zh not_active IP Right Cessation
- 2005-05-23 WO PCT/JP2005/009809 patent/WO2005114237A1/en active IP Right Grant
- 2005-05-23 EP EP05743583A patent/EP1756605B1/de not_active Not-in-force
- 2005-05-23 AT AT05743583T patent/ATE377767T1/de not_active IP Right Cessation
- 2005-05-23 JP JP2006519568A patent/JP3911007B1/ja not_active Expired - Fee Related
- 2005-05-23 DE DE602005003225T patent/DE602005003225T2/de active Active
- 2005-05-23 KR KR1020067024540A patent/KR20070020247A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
WO2005114237A1 (en) | 2005-12-01 |
US20050262412A1 (en) | 2005-11-24 |
EP1756605A1 (de) | 2007-02-28 |
TW200610082A (en) | 2006-03-16 |
KR20070020247A (ko) | 2007-02-20 |
DE602005003225T2 (de) | 2008-08-28 |
JP2008519247A (ja) | 2008-06-05 |
TWI352211B (en) | 2011-11-11 |
US7210087B2 (en) | 2007-04-24 |
JP3911007B1 (ja) | 2007-05-09 |
DE602005003225D1 (de) | 2007-12-20 |
EP1756605B1 (de) | 2007-11-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |