ATE354130T1 - Verfahren und einrichtung zum transferieren von daten zwischen einem hauptspeicher und einer speichereinrichtung - Google Patents

Verfahren und einrichtung zum transferieren von daten zwischen einem hauptspeicher und einer speichereinrichtung

Info

Publication number
ATE354130T1
ATE354130T1 AT04733418T AT04733418T ATE354130T1 AT E354130 T1 ATE354130 T1 AT E354130T1 AT 04733418 T AT04733418 T AT 04733418T AT 04733418 T AT04733418 T AT 04733418T AT E354130 T1 ATE354130 T1 AT E354130T1
Authority
AT
Austria
Prior art keywords
main memory
data
storage
storage device
way
Prior art date
Application number
AT04733418T
Other languages
English (en)
Inventor
Niekerk Paulus A W Van
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE354130T1 publication Critical patent/ATE354130T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT04733418T 2003-05-26 2004-05-17 Verfahren und einrichtung zum transferieren von daten zwischen einem hauptspeicher und einer speichereinrichtung ATE354130T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03101516 2003-05-26

Publications (1)

Publication Number Publication Date
ATE354130T1 true ATE354130T1 (de) 2007-03-15

Family

ID=33462213

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04733418T ATE354130T1 (de) 2003-05-26 2004-05-17 Verfahren und einrichtung zum transferieren von daten zwischen einem hauptspeicher und einer speichereinrichtung

Country Status (8)

Country Link
US (1) US20070011398A1 (de)
EP (1) EP1631911B1 (de)
JP (1) JP2007501473A (de)
KR (1) KR20060017816A (de)
CN (1) CN1795442A (de)
AT (1) ATE354130T1 (de)
DE (1) DE602004004780T2 (de)
WO (1) WO2004104846A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5076967B2 (ja) * 2008-02-27 2012-11-21 富士通株式会社 情報処理システム、情報処理システムの制御方法、および情報処理システムの制御プログラム
JP5226341B2 (ja) * 2008-02-27 2013-07-03 富士通株式会社 チャネル装置、情報処理システム、及びデータ転送方法
US8074113B2 (en) * 2009-03-10 2011-12-06 Emulex Design & Manufacturing Corporation System and method for data protection against power failure during sector remapping
US10095433B1 (en) 2012-10-24 2018-10-09 Western Digital Technologies, Inc. Out-of-order data transfer mechanisms for data storage systems
US10049061B2 (en) * 2012-11-12 2018-08-14 International Business Machines Corporation Active memory device gather, scatter, and filter
US9338057B2 (en) * 2013-10-30 2016-05-10 Netapp, Inc. Techniques for searching data associated with devices in a heterogeneous data center
US9990298B2 (en) * 2014-05-12 2018-06-05 Western Digital Technologies, Inc System and method for caching solid state device read request results
US9818170B2 (en) * 2014-12-10 2017-11-14 Qualcomm Incorporated Processing unaligned block transfer operations
US10956245B1 (en) * 2017-07-28 2021-03-23 EMC IP Holding Company LLC Storage system with host-directed error scanning of solid-state storage devices
CN109684140B (zh) * 2018-12-11 2022-07-01 广东浪潮大数据研究有限公司 一种慢盘检测方法、装置、设备及计算机可读存储介质
US11061676B2 (en) 2019-04-24 2021-07-13 International Business Machines Corporation Scatter gather using key-value store
JP6997235B2 (ja) * 2020-02-19 2022-01-17 株式会社日立製作所 データ転送システム
CN113031876B (zh) * 2021-03-31 2024-04-09 深信服科技股份有限公司 一种数据处理方法、装置、设备及可读存储介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4930065A (en) * 1987-08-20 1990-05-29 David Computer Corporation Automatic data channels for a computer system
GB2270780A (en) * 1992-09-21 1994-03-23 Ibm Scatter-gather in data processing systems.
US5802546A (en) * 1995-12-13 1998-09-01 International Business Machines Corp. Status handling for transfer of data blocks between a local side and a host side
US6021462A (en) * 1997-08-29 2000-02-01 Apple Computer, Inc. Methods and apparatus for system memory efficient disk access to a raid system using stripe control information
WO1999034273A2 (en) * 1997-12-30 1999-07-08 Lsi Logic Corporation Automated dual scatter/gather list dma
US7155569B2 (en) * 2001-02-28 2006-12-26 Lsi Logic Corporation Method for raid striped I/O request generation using a shared scatter gather list

Also Published As

Publication number Publication date
KR20060017816A (ko) 2006-02-27
JP2007501473A (ja) 2007-01-25
US20070011398A1 (en) 2007-01-11
DE602004004780T2 (de) 2007-12-06
WO2004104846A2 (en) 2004-12-02
WO2004104846A3 (en) 2005-01-13
EP1631911A2 (de) 2006-03-08
CN1795442A (zh) 2006-06-28
DE602004004780D1 (de) 2007-03-29
EP1631911B1 (de) 2007-02-14

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