WO1999034273A2

WO1999034273A2 - Automated dual scatter/gather list dma

Info

Publication number: WO1999034273A2
Application number: PCT/US1998/026830
Authority: WO
Inventors: Keith W. Holt; Bret S. Weber
Original assignee: Lsi Logic Corporation
Priority date: 1997-12-30
Filing date: 1998-12-16
Publication date: 1999-07-08
Also published as: WO1999034273A3

Abstract

A DMA controller (100) useful in a host adapter (106) which adapts signals on its local bus (152) to those of a host system (104). The DMA controller of the present invention has two addressing engines each capable of operating on an independent scatter/gather list. A first addressing engine (200) in the controller is provieded with a first scatter/gather list for generating addresses on the host bus. The second addressing engine (220) in the controller is provided with a second scatter/gather list, independent of the first, for generating addresses on the local bus of the host adapter. A sequencer block (230) in the DMA controller coordinates the operation of the two DMA addressing engines so as to perform a DMA transfer. The descriptors in the independent scatter/gather lists need not be combined as previously known in the art to create a composite scatter/gather list wherein descriptors are created for the least common size of the corresponding source and destination descriptors. The DMA of the present invention thereby improves host adapter performance by reducing computation overhead in the host adapter's local processor required for generating the composite scatter/gather list and also permits each scatter/gather list to optimize block sizes for efficient burst transfers on the corresponding bus.

Description

AUTOMATED DUAL SCATTER/GATHER LIST DMA

1. Field of the Invention

The invention relates to host adapter or I/O interface devices and in particular to host adapters connected directly to a host system bus wherein the adapters use dual scatter/gather lists to exchange information between the host system memory and local memory associated with the host adapter in a DMA transfer.

2. Discussion of Related Art Host computing systems generally include a system bus in which I/O interface circuits are inserted to connect the host system to peripheral I/O devices. Such circuits are often referred to as host adapters, I/O interfaces, I/O processors (IOP) and other equivalent terms and acronyms. It is known in the art to provide significant processing intelligence within host adapters. Intelligent host adapters may include significant local processing power and local memory used for processing of host I/O requests and for control of attached I/O devices.

A common feature of most such adapters is the frequent need to exchange data with the host system over the system bus. The Peripheral Component Interconnect (PCI) bus has become a popular system bus for direct connection of such host adapters to the host system. In such system bus configurations the host system may directly access the local memory of the host adapter. In like manner the host adapter may directly access the memory of the host system. Using such direct access to one another's memory, it is common to use direct memory access (DMA) components in host adapters to perform the requisite transfers of data with minimal overhead imposed on the general purpose processing power of both the host system and the host adapter.

It is known to use scatter/gather DMA techniques to permit flexibility in the distribution of data to be exchanged between a source and destination in a DMA transfer. Such scatter/gather techniques enable a DMA to retrieve data for the transfer from non-contiguous memory locations in the source memory (gather) and to store the retrieved data in non-contiguous locations of the destination memory (scatter). As presently known in the art, scatter/gather DMA devices use a single list that specifies to the DMA transfer circuits (DMA engine) a first source block of data to be retrieved, a corresponding, equal sized, destination block into which the retrieved data is to be stored, and a length for the transfer of that block. A next pair of source and destination locations and length is then processed and so on. A list of such scatter/gather blocks therefore defines the complete transfer to be made. The entries of the scatter/gather list are interleaved providing a source block specification, its corresponding destination block specification, and the length of the block to be transferred.

In general, a host adapter performs I/O operations with the attached I/O peripheral in response to receipt of an I/O request from the host system. Data is generally transferred between the host system memory and the local memory of the host adapter. For example, in processing a write request, the data to be written is transferred from the host system memory to the local memory of the host adapter (via DMA) and then on to the attached I/O device. In processing a read request, the requested data is retrieved or derived from the attached I/O device into the local memory of the host adapter and then transferred from the host adapter local memory to the host system memory (again, via DMA).

In processing of a host I/O request, the host adapter generally constructs a scatter/gather DMA block list to define the entire transfer required between the adapter's local memory and the host system's memory. As used in host adapters directly connected to a host system bus, current techniques and DMA designs require construction of a composite scatter/gather list that identifies pairs of corresponding source and destination blocks interleaved as described above wherein each block to be transferred is constructed in the scatter/gather list to have a least common block length. The scattered blocks in the source memory may not have the same size as the scattered blocks in the destination memory. Though the total size of all the blocks would be equal, the individual portions to be exchanged may not be. For example, where the host adapter is a caching storage controller, a read operation from the host system would cause the host adapter to retrieve the requested data from the storage peripheral device attached thereto. The retrieved data is stored in non-contiguous local buffer memory (typically a cache memory). Once so retrieved into the adapter's local memory, a composite DMA scatter/gather list is constructed to transfer the data in cache (local memory) to an identified set of memory locations in the host system. A write request from the host system is processed in a similar manner by transferring data from the host system's memory to the cache of the storage controller using a composite scatter/gather list constructed by the storage controller. A composite scatter/gather list is constructed (e.g., in the interleaved manner described above) by determining the largest common sizes which may be transferred in one continuous DMA operation without crossing a boundary of either a source block or a destination block. It will be understood by those skilled in the art that, as used herein, "block" is used to refer to a contiguous portion of either the source memory locations or the destination memory locations. "Block" as used herein is not intended to denote any particular block size associated with a particular I/O devices such as fixed size blocks associated with storage devices. "Block" as used herein rather refers to a contiguous portion of a source or destination memory into which, or from which, data is transferred in a DMA transfer. Construction of such composite scatter/gather lists constitutes overhead processing utilizing valuable processing power of the host adapter. Cumulative effects of excessive overhead processing within the host adapter can negatively impact the overall performance of the storage subsystem. It can be seen from the above discussion that a need exists for an improved architecture for host adapters to perform scatter/gather DMA operations in transferring information between a host system and a host adapter.

3. Summary of the Invention The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing a DMA design which uses two DMA addressing engines operating in close cooperation in a DMA channel to transfer data from a source to a destination using independent scatter/gather lists for the source and destination. In particular, the present invention uses a first scatter/gather list to identify blocks of data to be transferred from the source memory locations and a second scatter/gather list to identify blocks in the destination memory to which the data is transferred. In the preferred embodiment, two independent DMA engines are processing the lists independently to complete the requested transfer. A sequence control element of the DMA controller coordinates the operations of the independent DMA addressing engines to perform the desired transfer from source to destination. Those skilled in the art will recognize variants of this preferred embodiment wherein, for example, a single DMA engine may process the two scatter/gather lists. Or, for example, two nominally independent DMA channels, each with an associated DMA addressing engine, may be configured to operate in close cooperation. In all such alternative embodiments of the present invention, two scatter/gather lists are processed by the DMA controller, a first for the source of the transfer and a second for the destination of the transfer. The present invention obviates the need for the host adapter to use valuable processing power to construct a composite scatter/gather list. Rather, a pre-existing scatter/gather lists for the source memory and for the destination memory are used. Such pre-existing scatter/gather lists are often generated for other processing purposes within the host adapter or within the host system. The total transfer length described by the source scatter/gather list may be equal to the total transfer length described by the destination scatter/gather (though the two lists need not describe equal total lengths). However, the individual memory blocks defined by individual elements of the lists may be of varying sizes as appropriate to the memory layout in each of the source and destination memories. In the preferred embodiment of the present invention, the scatter/gather list associated with the host system is constructed by the host system and provided to the host adapter DMA via 120 shared memory access. The host adapter's local scatter/gather list is preferably pre-defined (constructed by the host adapter's processor and preferably resides locally within the host adapter.

Though not exclusively so, the present invention is well suited to I20 compatible host adapters. I20 standards are often applied in conjunction with PCI bus interfaces between host systems and host adapters operable therein. An I20 host adapter and a host system often share access to one another's memories via the connecting PCI bus. Further, I20 compatible host adapters communicate with the host systems via standard queue definitions which include scatter/gather list data structures to describe memory buffers associated with an I/O request. For example, a host read request supplies a scatter/gather list to be used by the host adapter for moving the requested data to the identified host memory buffers (blocks). Or a host write request supplies a scatter/gather list identifying the data blocks in host memory which are to be transferred to the host adapter for eventual transfer to the attached peripheral I/O device.

These I20 standard scatter gather lists are used directly by the DMA architecture of the present invention. Rather than construct a composite scatter/gather list using such pre-existing lists as input thereto, the present invention uses the pre-existing lists essentially "as is." Depending on a number of I20 implementation, configuration and operation details well known to those skilled in the art, the host adapter preferably uses the host system supplied scatter/gather list without moving it from the shared memory into which the host system placed the list. More specifically, the dual scatter/gather DMA of the present invention includes a first pointer value to point to a source scatter/gather list and a second pointer value to point at a destination scatter/gather list. These pointer values are preferably stored as registers within the DMA controller. The pointer value registers are initialized (seeded) by host adapter software to point to source and destination scatter/gather lists appropriate for the desired transfer. Each element of the scatter/gather lists preferably includes an end flag (e.g., a bit) to indicate that it is the last element in the list describing a block to be transferred. The list of elements may be resident in contiguous memory or the elements (descriptors) may be themselves linked through non-contiguous memory in which case the descriptors include a link field to form the linked list with other descriptors. In either case, an aspect of the descriptors (i.e., a flag bit or a linked list pointer value) indicates whether the descriptor is the last in the chain. More generally, the descriptors in the scatter/gather lists may include an interrupt flag bit independent of the end of chain indicator. The interrupt flag bit indicates, if set, that the processor of the host adapter is to be interrupted to notify it of the completion of the corresponding block in the DMA transfer. This interrupt may be generated at the end of the chain of ^■ descriptors or intermediate in the chain of descriptors as defined by the interrupt flag bit independent of the end of chain indicator.

In application with an I20 compatible adapter, it may be preferable that the scatter/gather list format be compatible with the I2O specifications such that the DMA controller may directly utilize existing scatter/gather list formats. In such cases, it is preferred that the end flag of the present invention be stored and retrieved in a structure external to, but associated with, the scatter/gather list(s). As used herein, the end flag is referred to as being in the scatter/gather list regardless of where it is physically stored (i.e., whether physically stored in the scatter/gather list entries or in a meta-structure associated with the scatter/gather lists). When the DMA of the present invention begins the DMA transfer, a source address value and block counter are loaded from the first element of the source scatter/gather list and a destination address value and block counter are loaded from the first element of the destination scatter/gather list. As each unit of data is transferred by the DMA from source to destination, the two address values are updated as required (incremented or decremented as desired) and the counter values are decremented. When either of the destination or source block counter values are decremented to zero, the next element in the corresponding list is fetched to reload the corresponding address value and block counter for a next source or destination block. When all elements of both lists have been so processed, as indicated by the end flag set in an element of either list, the DMA transfer is complete.

It is therefore an object of the present invention to provide a DMA architecture which uses dual scatter/gather lists to define a DMA transfer. It is a further object of the present invention to provide a DMA architecture which reduces host adapter overhead processing to prepare a DMA transfer.

It is still a further object of the present invention to provide a DMA architecture which couples two DMA engines to operate on independent scatter/gather lists to perform a single DMA transfer.

It is yet a further object of the present invention to provide a dual scatter/gather list DMA engine in a host adapter which uses a first, host supplied scatter/gather list identifying host system memory blocks and a second host adapter supplied scatter/list identifying host adapter local memory blocks associated with a DMA transfer.

It is still yet a further object of the present invention to provide a dual scatter/gather list DMA engine in a host adapter which uses a first, host supplied scatter/gather list identifying host system memory blocks and a second host adapter supplied scatter/list identifying host adapter local memory blocks associated with a DMA transfer where corresponding elements of the lists do not define equal block sizes. The above and other objects, aspects, features, and advantages of the present invention will become apparent from the following description and the attached drawings.

4. Brief Description of the Drawings

FIG. 1 is a block diagram of a typical host adapter environment in which the DMA controller of the present invention may be advantageously applied;

FIG. 2 is a block diagram of the DMA controller of the present invention as shown applied in FIG. 1; and

FIG. 3 depicts tables describing exemplary construction of a composite scatter/gather list as is known in the art prior to the present invention.

5. Detailed Description of the Preferred Embodiments While the invention is susceptible to various modifications and alternative forms, a specific embodiment thereof has been shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that it is not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

FIG. 1 is a block diagram depicting a typical host system 104 connected to a host adapter 106 in which the DMA controller 100 of the present invention may be advantageously applied. In particular, host system 104 and host adapter 106 are connected via a common peripheral interface bus 102. In general, host adapter 106 processes I/O requests received from host system 104 via common bus 102. Host adapter 106 may be connected to external I/O peripheral devices (not shown) on which I/O operations are performed for the benefit of, and at the request of, host system 104. Host adapter 106 of FIG. 1 is intelligent in that it possesses significant local processing power to perform I/O processing with a minimum of overhead imposed on the host system 104. Such intelligent host adapters are often utilized for host interconnection to high performance storage subsystems or networks (as well as other application apparent to those skilled in the art). As noted above, bus 102 is preferably a PCI compatible bus.

However, those skilled in the art will recognize that any of several interface busses (direct connect or remote connection) may be utilized in conjunction with the DMA controller and associated methods of the present invention. A particular advantage of the PCI bus (but also provided by other bus architectures) is the symmetry permitted in the access. A master device anywhere on the bus may access a target device anywhere on the bus. The physical location of master and target with respect to the bus are irrelevant. Any device can perform at any given time in either the master role or the target role. Exemplary host system 104 further comprises a host CPU 120 and host memory 122 (as well as myriad other components not shown) connected via internal bus 150. PCI interface 124 serves to connect the devices on internal bus 150 to the PCI bus 102. Those skilled in the art will recognize that internal bus 150 (also commonly referred to as the processor bus) may be any of several standard busses depending upon the choice of components for host CPU 120. PCI interface 124 is typically a chip set selected to adapt the selected processor bus (150) to the PCI bus 124. Those skilled in the art will recognize a wide variety of such processor/PCI interface design choices.

Host adapter 106 shares the basic architectural design of host system 104 in that it comprises a local CPU 128 and local memory 130 connected via internal bus 152 (specific to the processor selected as local CPU 128). Devices on internal bus 152 are connected through DMA 100 to PCI bus 102 via PCI interface 126 and bus 154. Those skilled in the art will recognize DMA 100 as a pass-through DMA controller wherein busses 152 and 154 are joined by a FIFO within DMA 100. All accesses between devices on processor bus 152 and PCI interface 126 pass through DMA 100 and bus 154.

DMA 100 is preferably such a pass-through DMA controller. However, those skilled in the art will recognize that the features and aspects of the present invention are similarly applicable to so-called "fly-by" DMA controllers. Fly-by DMA controllers are characterized in that they reside on the same bus as all devices which may use the DMA channel. The fly-by DMA controller assumes control of the bus to exchange data between two devices on the bus. By contrast, a pass-through DMA controller is more akin to a bus bridge wherein transfers via DMA are performed on two electrically distinct busses via a FIFO within the DMA controller.

A key feature of the architecture of FIG. 1 , as noted above, is the symmetry of access. Devices within host system 104 (e.g., CPU 120 or DMA controllers not shown) may act as a PCI bus master in accessing the local memory within host adapter 106. In such transactions, devices in host adapter 106 perform in the role of PCI bus target. In other transactions, the roles may be reversed such that devices in host adapter 106 (e.g., CPU 128 via DMA 100) may act as masters initiating access to host memory 122. In such transactions, devices in host system 104 act in the role of PCI target. Dual scatter/gather list DMA 100 in host adapter 106 is a DMA controller in accordance with the present invention which is adapted to perform the exchange of information between local memory 130 and host memory 122. DMA 100 accesses local memory 130 via internal bus 152 and accesses host memory 122 indirectly through bus 154 via PCI bus 102 and PCI interfaces 126 and 124.

For example, in processing a write I/O request, DMA 100 retrieves information from host memory 122 and moves it to local memory 130 for further processing within host adapter 106. More particularly, local memory 130 may be, for example, a cache memory in a host adapter 106 used for storage subsystem management (e.g., RAID storage subsystem management). However, those skilled in the art will recognize that the local memory 130 may be any memory appropriate to the particular transfer, medium, and protocols implemented by a particular host adapter 106. The data to be written may be stored in host memory 122 in non-contiguous blocks. These locations are made known to host adapter 106 via a scatter/gather list provided by host system 104. In like manner, the locations in local memory 130 to which the blocks are to written may be non-contiguous (scattered throughout the memory). Read operations operate in a similar manner but in reverse. Specifically, a host system 104 read I/O request will request retrieval of particular blocks or types of data. In the case of a storage subsystem host adapter 106, the requested data, if not already present, is retrieved from the storage devices (not shown) and temporarily saved in local memory 130 (i.e., cache memory). The retrieved data may be scattered about within local memory 130. The locations in host memory 122 to which the retrieved data is to be transferred are independent of the local memory addresses and may likewise be non-contiguous. These locations are made known to host adapter 106 via a scatter/gather list provided by host system 104. The scattered locations within local memory 130 are known to DMA 100 via a scatter/gather list constructed within host adapter 106 by CPU 128.

DMA 100 is operable to exchange the requested data between local memory 130 of host adapter 106 and host memory 122. As is previously known in the art, CPU 128 may construct a composite scatter/gather list which joins the two supplied scatter/gather lists. However, so joining the scatter/lists requires processing overhead within host adapter 106. This overhead leads to inefficiency in the DMA transfer due to the composite list typically being larger than either list alone. In particular, as is taught in the art, such a composite list is built such that each entry includes a source location, a corresponding destination location, and a block size corresponding to both. Since the scattered block in host memory 122 and local memory 130 may not be of equal size, CPU 128 must calculate construct the composite list so as to define portions of source and destination blocks having equal sizes (a least common size). In addition to the processing overhead noted above, the formulation of a composite list may result in inefficient burst transfers occurring on the host or local busses if the address boundaries are not similarly aligned. In other words, the composite list constructed with least common size sub-blocks derived from the blocks defined in the source and destination lists may not optimally align the blocks for DMA burst efficiency as compared to the independent source and destination lists.

FIG. 3 shows an example of such a decomposition of a source scatter/gather list and a destination scatter/gather list to construct a composite scatter/gather list. A scatter/gather list for a source of the DMA exchange is shown as table 400. A scatter/gather list for a destination of the DMA exchange is shown as table 402. As can be see, the block sizes listed in the source scatter/gather list of table 400 are different from those of destination scatter/gather list of table 402 (though the total transfer size happens to be identical).

As is known in the art prior to the present invention, a composite scatter/gather list as shown by table 404 of FIG. 3 is constructed within host adapter 106 by CPU 128. The composite scatter/gather list of table 404 combines the source scatter/gather list table 400 entries and the destination scatter/gather list table 402 entries such that no single new composite table 404 entries spans a boundary of the block sizes defined by the two original tables 400 and 402.

DMA controller 100 of the present invention operates on two scatter/gather lists provided to it to obviate the need for CPU 128 to construct the composite list. A first DMA addressing engine (also referred to herein as DMA engine) within DMA 100 controls operation of DMA 100 to fetch information from source locations in accordance with the source scatter/gather list provided to. A second DMA addressing engine with DMA 100 of the present invention controls operation of DMA 100 to store the fetched data at destination locations in accordance with the destination scatter/gather list provided to it. The two DMA engines in DMA 100 of the present invention are independently operable on each of two independent scatter/gather lists.

FIG. 2 is a block diagram depicting additional detail of DMA 100 of FIG. 1. In particular, DMA 100 includes two DMA addressing engines (also referred to herein as DMA engines). Host DMA addressing engine 200 controls address generation for host memory 122 addresses for the DMA transfer request. Local DMA addressing engine 220 controls address generation for local memory 130 accesses in the DMA transfer request. Each engine (200 and 220), per se, is operable independent of the other with regard to address generation. DMA transfer coupling sequencer 230 synchronizes the address generation and bus control to apply the addresses generated by the DMA engines to busses 152 and 154 and to apply signals thereto to fetch or store data associated with the generated addresses. DMA transfer coupling sequencer 230 and the DMA engines (200 and 220) are connected via internal busses 252 and 254, respectively.

DMA transfer coupling sequencer 230, in conjunction with the DMA addressing engines 200 and 220, effectuate the exchange of data between local memory 130 and host memory 122 in accordance with two independent scatter/gather lists. S/G fetch block 226 in local DMA addressing engine 220 is used to fetch an entry from a scatter/gather list and provide it to the appropriate DMA addressing engine 200 or 220 via bus 250. A first scatter/gather list is used to determine the addresses generated by host memory DMA addressing engine 200. A second scatter/gather list is used to determine the addresses generated by local memory DMA addressing engine 220.

As discussed herein, several alternative embodiments are intended within the scope of the present invention as regards the location and structure of the scatter/gather lists and meta-data associated therewith. For example, the host scatter/gather list may reside in local memory 130 or host memory 122. Or, for example, the host scatter/gather list may be compatible with I20 standard structures directly used by DMA 100 of the present invention. In the preferred embodiment, local memory 130 contains a meta-data structure which points to elements of both scatter/gather lists and includes control information regarding each element of the list (e.g., end of transfer flags, automated reply flags, etc.). S/G fetch block 226 is therefore depicted as physically associated with the local DMA addressing engine 220. Preferably it accesses information in the meta-data structure which directs its further fetching of data from either local memory 130 via bus 152 or from host memory 122 via bus 152, FIFO 240, bus 154, PCI interface 126, etc. Alternatively, all scatter/gather list information, including host scatter/gather list entries, may be copied or otherwise generated or stored in local memory 130. In such embodiments, S/G fetch block 226 simply accesses all requisite information directly from local memory 130 via bus 152.

DMA transfer coupling sequencer 230 in conjunction with S/G fetch block 236 initializes each DMA engine with an address and block count from the first entry of the corresponding scatter/gather list. Specifically, host memory DMA addressing engine 200 receives the start address and block count from the first entry of the host scatter/gather list. In like manner, local memory DMA addressing engine 220 receives the start address and block count from the first entry of the local scatter/gather list. DMA transfer coupling sequencer 230 then starts the DMA transfer process and monitors status from each of the DMA engines to determine when its present block count is exhausted (i.e., decremented to zero).

In particular, DMA transfer coupling sequencer 230 exchanges control signals with host DMA addressing engine 200 via bus 252 and with local DMA addressing engine 220 via bus 254. Control signals include a signal to instruct the DMA addressing engine to load new values, via bus 250, into the address and length counters to start a new block. A zero count indicator is provided from each DMA addressing engine to the sequencer 230 to inform the sequencer when a particular block transfer has completed on the corresponding DMA addressing engine. In addition, a status signal from each DMA addressing engine indicates when the corresponding addressing engine has completed the transfer of one unit of data (of whatever unit size is appropriate to the corresponding bus and application). Sequencer 230 uses this information to coordinate the transfer by the opposite DMA addressing engine. A signal from the sequencer 230 to each addressing engine determines the timing and sequencing of the data transfers on each of the DMA addressing engines.

Each DMA addressing engine includes an address counter block (202 and 222 in engines 200 and 220, respectively) and a length counter block (204 and 224 in engines 200 and 220, respectively). The address counter block is loaded with the start address for a block to be transferred as determined by the corresponding data in the scatter/gather list element used to control the corresponding addressing engine. The address counter block increments for each unit of data transferred (incremented by an amount appropriate for the unit data size in the particular DMA 100 application). The length counter blocks of the DMA engines are loaded with the length value for each block to be transferred and is decremented (by an appropriate value) for each unit of data transferred between the host memory and the local memory.

All data transfers between the two memory are applied to the opposite bus through FIFO 240 in DMA controller 100. The FIFO serves to buffer each side from timing constraints of the other's bus standards. In addition, FIFO 240 allows bus size matching. For example if BUS 152 is a 32-bit wide data bus while bus 154 is 64-bits wide, two transfers are made between FIFO 240 and bus 152 for every one transfer between FIFO 240 and bus 154. Status signals from FIFO 240 applied to bus 256 indicate to sequencer 230 the number of units of data present in FIFO 240 at any time.

When DMA transfer coupling sequencer 230 senses that one of the DMA engines has exhausted its present block count, a next entry from the corresponding scatter/gather list is retrieved and the DMA engine restarted with the address and count value from the next entry loaded. Each entry in the scatter/gather lists includes a flag bit to indicate whether it is the last entry in the list. DMA transfer coupling sequencer 230 monitors this flag bit in the entry being processed when a DMA engine exhausts its present transfer block count. If the flag is set in the entry presently being processed, indicating the end of the corresponding scatter/gather list, DMA transfer coupling sequencer 230 terminates the transfer operation to thereby successfully complete the requested data exchange between the host memory and local memory.

Those skilled in the art will recognize that the flag may be set in an entry of either the source scatter/gather list, or the destination scatter/gather list, or both. When both the source and destination scatter/gather lists define equal total transfer lengths, the end of transfer flag may be set in the last entry of either or both scatter/gather lists. It is also common that a transfer source may define a total transfer length which is less than the total length defined by the destination scatter/gather list. For example, a destination scatter/gather list may define a maximum permissible transfer with respect to the destination memory or with respect to other limitations of an attached peripheral device or the host system. The source scatter/gather list therefore defines a desired transfer length for the particular transfer to be performed. In such a case, the last entry in the source scatter/gather list would typically be sensed by DMA transfer coupling sequencer 230 to complete the requested exchange. The last entry in the destination scatter/gather list (a list which may define a maximum allowed transfer) is typically not encountered other than in exception conditions where a requested source for a transfer exceeds the maximum transfer allowed by the particular destination. The converse of the above may also apply. That is, the total length defined by the source scatter/gather list may exceed the total length defined by the destination scatter/gather list. In such cases the DMA transfer is simply completed in two separate operations regardless of the direction of the transfer.

While the invention has been illustrated and described in the drawings and foregoing description, such illustration and description is to be considered as exemplary and not restrictive in character, it being understood that only the preferred embodiment and minor variants thereof have been shown and described and that all changes and modifications that come within the spirit of the invention are desired to be protected.

Claims

CLAIMS What is claimed is:

1. A DMA controller comprising: a first DMA engine associated with a host memory scatter/gather list; a second DMA engine associated with a local memory scatter/gather list; and control means coupled to said first DMA engine and to said second

DMA engine for controlling operation of said first DMA engine and said second DMA engine to exchange data between said host memory, in accordance with said host memory scatter/gather list, and said local memory, in accordance with said local memory scatter/gather list.

2. The DMA controller of claim 1 wherein a portion of said host memory scatter/gather list resides in said host memory and wherein said first DMA engine includes: means for accessing said host memory to retrieve said host memory scatter/gather list.

3. The DMA controller of claim 1 wherein an element in said host memory scatter/gather list includes an end of transfer indicator and wherein said control means includes: means for detecting said end of transfer indicator to thereby complete said exchange of data.

4. The DMA controller of claim 1 wherein an element in said local memory scatter/gather list includes an end of transfer indicator and wherein said control means includes: means for detecting said end of transfer indicator to thereby complete said exchange of data.

5. The DMA controller of claim 1 wherein said first DMA engine includes: a host transfer counter register; and a host transfer address register, and wherein said second DMA engine includes: a local transfer counter register; and a local transfer address register.

6. The DMA controller of claim 5 wherein said control means includes: means for loading a host start address value into said host transfer address register, said host start address value being retrieved from a first entry in said host memory scatter/gather list; means for loading a local start address value into said local transfer address register, said local start address value being retrieved from a first entry in said local memory scatter/gather list; means for loading a host start count value into said host transfer counter register, said host start count value being retrieved from a first entry in said host memory scatter/gather list; and means for loading a local start count value into said local transfer counter register, said local start counter value being retrieved from a first entry in said local memory scatter/gather list.

7. The DMA controller of claim 6 wherein said control means further includes: means for decrementing said host transfer counter in response to each unit of information exchanged between said host memory and said local memory; and means for decrementing said local transfer counter in response to each unit of information exchanged between said host memory and said local memory.

8. The DMA controller of claim 7 wherein said control means further includes: means for detecting a zero value in said host transfer counter; host reload means, responsive to said means for detecting a zero value in said host transfer counter, for loading a host start address value into said host transfer address register and for loading a host start count value into said host transfer counter register, said host start address value and said host start count value being retrieved from a next entry in said host memory scatter/gather list; means for detecting a zero value in said local transfer counter; local reload means, responsive to said means for detecting a zero value in said local transfer counter, for loading a local start address value into said local transfer address register and for loading a local start count value into said local transfer counter register, said local start address value and said local start count value being retrieved from a next entry in said local memory scatter/gather list.

9. A method operable within a DMA controller to utilize a dual scatter/gather lists in performing a DMA transfer, said method comprising the steps of: loading a source counter in said DMA controller in accordance with a first source scatter/gather entry from a source scatter/gather list wherein said first source scatter/gather entry includes a source block start address and a source block length count; loading a destination counter in said DMA controller in accordance with a first destination scatter/gather entry from a destination scatter/gather list wherein first destination said scatter/gather entry includes a destination block start address and a destination block length count; transferring information from locations starting at said source block start address to locations starting at said destination block start address; and decrementing said source counter and said destination counter in response to the transfer of information.

10. The method of claim 9 further comprising the steps of: detecting a zero value in said source counter; reloading said source counter with a next source block count value, responsive to the detection of said zero value in said source counter, said next source block count value being retrieved from a next source scatter/gather entry from said source scatter/gather list, wherein said next source scatter/gather entry includes a next source block start address and said next source block length count; and continuing the transfer of information from locations starting at said next source block start address.

11. The method of claim 10 further comprising the steps of: detecting an end of transfer indicator in said next source scatter/gather list entry; and terminating the transfer of information in response to the detection of said end of transfer indicator.

12. The method of claim 9 further comprising the steps of: detecting a zero value in said destination counter; reloading said destination counter with a next destination block count value, responsive to the detection of said zero value in said destination counter, said next destination block count value being retrieved from a next destination scatter/gather entry from said destination scatter/gather list, wherein said next destination scatter/gather entry includes a next destination block start address and said next destination block length count; and continuing the transfer of information to locations starting at said next destination block start address.

13. The method of claim 12 further comprising the steps of: detecting an end of transfer indicator in said next destination scatter/gather list entry; and terminating the transfer of information in response to the detection of said end of transfer indicator.