WO1999034273A3 - Automated dual scatter/gather list dma - Google Patents

Automated dual scatter/gather list dma Download PDF

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Publication number
WO1999034273A3
WO1999034273A3 PCT/US1998/026830 US9826830W WO9934273A3 WO 1999034273 A3 WO1999034273 A3 WO 1999034273A3 US 9826830 W US9826830 W US 9826830W WO 9934273 A3 WO9934273 A3 WO 9934273A3
Authority
WO
WIPO (PCT)
Prior art keywords
scatter
gather list
dma
addressing
controller
Prior art date
Application number
PCT/US1998/026830
Other languages
French (fr)
Other versions
WO1999034273A2 (en
Inventor
Keith W Holt
Bret S Weber
Original Assignee
Lsi Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Corp filed Critical Lsi Logic Corp
Publication of WO1999034273A2 publication Critical patent/WO1999034273A2/en
Publication of WO1999034273A3 publication Critical patent/WO1999034273A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

A DMA controller (100) useful in a host adapter (106) which adapts signals on its local bus (152) to those of a host system (104). The DMA controller of the present invention has two addressing engines each capable of operating on an independent scatter/gather list. A first addressing engine (200) in the controller is provieded with a first scatter/gather list for generating addresses on the host bus. The second addressing engine (220) in the controller is provided with a second scatter/gather list, independent of the first, for generating addresses on the local bus of the host adapter. A sequencer block (230) in the DMA controller coordinates the operation of the two DMA addressing engines so as to perform a DMA transfer. The descriptors in the independent scatter/gather lists need not be combined as previously known in the art to create a composite scatter/gather list wherein descriptors are created for the least common size of the corresponding source and destination descriptors. The DMA of the present invention thereby improves host adapter performance by reducing computation overhead in the host adapter's local processor required for generating the composite scatter/gather list and also permits each scatter/gather list to optimize block sizes for efficient burst transfers on the corresponding bus.
PCT/US1998/026830 1997-12-30 1998-12-16 Automated dual scatter/gather list dma WO1999034273A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US82297A 1997-12-30 1997-12-30
US09/000,822 1997-12-30

Publications (2)

Publication Number Publication Date
WO1999034273A2 WO1999034273A2 (en) 1999-07-08
WO1999034273A3 true WO1999034273A3 (en) 1999-09-23

Family

ID=21693157

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/026830 WO1999034273A2 (en) 1997-12-30 1998-12-16 Automated dual scatter/gather list dma

Country Status (1)

Country Link
WO (1) WO1999034273A2 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6718405B2 (en) * 2001-09-20 2004-04-06 Lsi Logic Corporation Hardware chain pull
CN1764905A (en) * 2003-03-25 2006-04-26 皇家飞利浦电子股份有限公司 Method of addressing data in a shared memory by means of an offset
KR20060017816A (en) * 2003-05-26 2006-02-27 코닌클리케 필립스 일렉트로닉스 엔.브이. Method and device for transferring data between a main memory and a storage device
CN1306594C (en) * 2005-03-08 2007-03-21 北京中星微电子有限公司 Graphic engine chip and its using method
JP5076967B2 (en) * 2008-02-27 2012-11-21 富士通株式会社 Information processing system, information processing system control method, and information processing system control program
JP5226341B2 (en) 2008-02-27 2013-07-03 富士通株式会社 Channel device, information processing system, and data transfer method
JP5482230B2 (en) 2010-01-25 2014-05-07 富士通株式会社 COMMUNICATION DEVICE, INFORMATION PROCESSING DEVICE, COMMUNICATION DEVICE CONTROL METHOD, AND CONTROL PROGRAM
US10049061B2 (en) 2012-11-12 2018-08-14 International Business Machines Corporation Active memory device gather, scatter, and filter
US11074169B2 (en) * 2013-07-03 2021-07-27 Micron Technology, Inc. Programmed memory controlled data movement and timing within a main memory device
US9818170B2 (en) * 2014-12-10 2017-11-14 Qualcomm Incorporated Processing unaligned block transfer operations
US10375168B2 (en) 2016-05-31 2019-08-06 Veritas Technologies Llc Throughput in openfabrics environments
US11449367B2 (en) 2019-02-27 2022-09-20 International Business Machines Corporation Functional completion when retrying a non-interruptible instruction in a bi-modal execution environment
US10698854B1 (en) * 2019-02-27 2020-06-30 International Business Machines Corporation Secure and efficient application data processing
US11003606B2 (en) 2019-06-21 2021-05-11 Microchip Technology Incorporated DMA-scatter and gather operations for non-contiguous memory
US11023400B1 (en) 2020-01-20 2021-06-01 International Business Machines Corporation High performance DMA transfers in host bus adapters

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0756234A1 (en) * 1995-07-24 1997-01-29 Symbios Logic Inc. Method and apparatus for transferring data in a controller having a centralized memory
JPH09160862A (en) * 1995-12-13 1997-06-20 Internatl Business Mach Corp <Ibm> Status processing system for transfer of data block between local side and host side

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0756234A1 (en) * 1995-07-24 1997-01-29 Symbios Logic Inc. Method and apparatus for transferring data in a controller having a centralized memory
JPH09160862A (en) * 1995-12-13 1997-06-20 Internatl Business Mach Corp <Ibm> Status processing system for transfer of data block between local side and host side
US5802546A (en) * 1995-12-13 1998-09-01 International Business Machines Corp. Status handling for transfer of data blocks between a local side and a host side

Also Published As

Publication number Publication date
WO1999034273A2 (en) 1999-07-08

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