ATE310276T1 - Bus-brücke und system für mehrkanalübertragung von daten- und steuerinformationen - Google Patents

Bus-brücke und system für mehrkanalübertragung von daten- und steuerinformationen

Info

Publication number
ATE310276T1
ATE310276T1 AT01932961T AT01932961T ATE310276T1 AT E310276 T1 ATE310276 T1 AT E310276T1 AT 01932961 T AT01932961 T AT 01932961T AT 01932961 T AT01932961 T AT 01932961T AT E310276 T1 ATE310276 T1 AT E310276T1
Authority
AT
Austria
Prior art keywords
data
control information
channel transmission
bus bridge
bridge
Prior art date
Application number
AT01932961T
Other languages
English (en)
Inventor
Sundar Rajan
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE310276T1 publication Critical patent/ATE310276T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/14—Multichannel or multilink protocols

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Security & Cryptography (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
  • Small-Scale Networks (AREA)
  • Selective Calling Equipment (AREA)
AT01932961T 2000-05-03 2001-05-03 Bus-brücke und system für mehrkanalübertragung von daten- und steuerinformationen ATE310276T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/564,592 US7107383B1 (en) 2000-05-03 2000-05-03 Method and system for multi-channel transfer of data and control information
PCT/US2001/014336 WO2001084330A2 (en) 2000-05-03 2001-05-03 A method and system for multi-channel transfer of data and control information

Publications (1)

Publication Number Publication Date
ATE310276T1 true ATE310276T1 (de) 2005-12-15

Family

ID=24255107

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01932961T ATE310276T1 (de) 2000-05-03 2001-05-03 Bus-brücke und system für mehrkanalübertragung von daten- und steuerinformationen

Country Status (6)

Country Link
US (2) US7107383B1 (de)
EP (1) EP1279103B1 (de)
AT (1) ATE310276T1 (de)
AU (1) AU2001259440A1 (de)
DE (1) DE60115010T2 (de)
WO (1) WO2001084330A2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
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US7107383B1 (en) * 2000-05-03 2006-09-12 Broadcom Corporation Method and system for multi-channel transfer of data and control information
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
US6959372B1 (en) * 2002-02-19 2005-10-25 Cogent Chipware Inc. Processor cluster architecture and associated parallel processing methods
US7096304B2 (en) * 2003-12-31 2006-08-22 Micron Technology, Inc. Apparatus and method for managing voltage buses
US7929368B2 (en) 2008-12-30 2011-04-19 Micron Technology, Inc. Variable memory refresh devices and methods
US8615621B2 (en) * 2009-12-24 2013-12-24 St-Ericsson Sa Memory management
TW201308200A (zh) * 2011-08-12 2013-02-16 Ite Tech Inc 橋接裝置及其資料預取及丟棄之方法
US9838500B1 (en) * 2014-03-11 2017-12-05 Marvell Israel (M.I.S.L) Ltd. Network device and method for packet processing

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EP0654743A1 (de) 1993-11-19 1995-05-24 International Business Machines Corporation Rechnersystem mit einem lokalen Bus eines Digitalsignalprozessors
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US5911055A (en) * 1996-06-05 1999-06-08 Compaq Computer Corporation Using subordinate bus devices that are connected to a common bus
GB9613473D0 (en) 1996-06-27 1996-08-28 Mitel Corp ATM cell transmit priority allocator
US5983291A (en) * 1996-09-24 1999-11-09 Cirrus Logic, Inc. System for storing each of streams of data bits corresponding from a separator thereby allowing an input port accommodating plurality of data frame sub-functions concurrently
US5774683A (en) * 1996-10-21 1998-06-30 Advanced Micro Devices, Inc. Interconnect bus configured to implement multiple transfer protocols
US5805845A (en) * 1996-10-21 1998-09-08 Advanced Micro Devices, Inc. Method for loading memory with program and data information from PC memory across a bridging bus
US5832245A (en) * 1996-10-21 1998-11-03 Advanced Micro Devices, Inc. Method for isochronous flow control across an inter-chip bus
EP0859320B1 (de) * 1996-10-31 2003-05-02 Texas Instruments Incorporated Eine konfigurierbare Erweiterungsbussteuereinheit
US5761462A (en) * 1996-12-13 1998-06-02 International Business Machines Corporation Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data-processing system
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US6108736A (en) * 1997-09-22 2000-08-22 Intel Corporation System and method of flow control for a high speed bus
US6189063B1 (en) * 1997-09-30 2001-02-13 Texas Instruments Incorporated Method and apparatus for intelligent configuration register access on a PCI to PCI bridge
US5996034A (en) * 1997-10-14 1999-11-30 Advanced Micro Devices, Inc. Bus bridge verification system including device independent bus monitors
US5964859A (en) * 1997-10-30 1999-10-12 Advanced Micro Devices, Inc. Allocatable post and prefetch buffers for bus bridges
US6112311A (en) * 1998-02-20 2000-08-29 International Business Machines Corporation Bridge failover system
JPH11238030A (ja) * 1998-02-20 1999-08-31 Mitsubishi Electric Corp Ｐｃｉ−ｐｃｉブリッジおよびそのための先入れ先出しメモリ
US6081863A (en) * 1998-03-13 2000-06-27 International Business Machines Corporation Method and system for supporting multiple peripheral component interconnect PCI buses by a single PCI host bridge within a computer system
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US7107383B1 (en) 2000-05-03 2006-09-12 Broadcom Corporation Method and system for multi-channel transfer of data and control information
US6466541B1 (en) * 2000-05-31 2002-10-15 Fujitsu Network Communications, Inc. Cell pacing on a network link employing a rate-based flow control protocol with underlying credit-based flow control mechanisms

Also Published As

Publication number Publication date
WO2001084330A3 (en) 2002-06-13
WO2001084330A2 (en) 2001-11-08
US7334074B2 (en) 2008-02-19
EP1279103B1 (de) 2005-11-16
DE60115010T2 (de) 2006-08-03
EP1279103A2 (de) 2003-01-29
DE60115010D1 (de) 2005-12-22
US20070016713A1 (en) 2007-01-18
AU2001259440A1 (en) 2001-11-12
US7107383B1 (en) 2006-09-12

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties