GB2337403A

GB2337403A - Data communication

Info

Publication number: GB2337403A
Application number: GB9810078A
Authority: GB
Inventors: Trevor Jones
Original assignee: GEN DATACOMM ADV RES; General Datacomm Inc
Current assignee: GEN DATACOMM ADV RES; General Datacomm Inc
Priority date: 1998-05-11
Filing date: 1998-05-11
Publication date: 1999-11-17
Also published as: GB9810078D0

Abstract

Data communication over a communication link e.g. SONET having a predetermined communication rate is "artificially" reduced by inhibiting transmission of data at intervals (20,22,23) or based on a measure of the actual data rate. This allows a network operator to make available a link having a communication capacity which is non-standard in a network which otherwise conforms to standard communication rates.

Description

2337403 DATA COMMUNICATION The present invention relates to data

communication, particularly, but not exclusively in an ATM network.

Telecommunications services generally operate over an underlying synchronous backbone network operating at a standard communication rate. For example, in an ATM network, ATM cells are typically transported by packing into SONET frames sent over optical fibre, SONET being a synchronous protocol. Standard data rates for SONET have been defined, standards in common use including 0C3 (155 Mbit/s) and OC 12 (622 Mbit/s). Since the links in a network backbone carry synchronous traffic at a standard data rate, normally a multiple of a common factor, combining links and interconnection between links is facilitated; practical networks do not therefore include non-standard links.

Data traffic from individual subscribers is usually multiplexed at various points so that a single 0C3 link, for example, may carry ATM cells from a large number of sources, the sources varying as calls are made and terminated. Larger volume subscribers may, however, have a requirement for a permanent connection of relatively large capacity. One way to achieve this is by means of permanent virtual circuits defined at the ATM level. Such connections, however, are suitable only for pre-defined pointto-point links.

Certain users may require a link of capacity approaching that of a standard link, without wishing to be restricted to use of pre-specified virtual paths or circuits defined at the ATM layer, in which case it becomes practical for the subscriber to connect directly to the telecommunications network nearer the core. For example, a subscriber requiring a permanent connection of 150 Mbit/s capacity may be permanently allocated exclusive use of a particular 0C3 link physically connected to an ATM switch integrated into the network.

With existing arrangements, there is no convenient way in which a dedicated link of non-standard 25 capacity can readily be provided for a user. For example, a user who requires a 60 Mbit/s capacity link would typically be allocated an 0C3 link. However, since the link may be used to carry ATM cells directed to multiple virtual paths and virtual channels, which may change under the user' s control, it is not straightforward to limit the usage made of the link to 60 MbitIs. Therefore, the telecommunications supplier may charge such a user a similar price for the link 5 as if a full 155 Mbit/s link were made available, which the user may find undesirable. Alternatively, a user who has requested a link of such lower capacity, for example 60 Mbit/s, and been charged a corresponding lower price, if provided with a standard 155 Mbit/s link, may proceed to make use of the fiffl physical link capacity, which can lead to possible unexpected excess traffic elsewhere in the network, and loss of revenue for the telecommunications supplier.

The inventor has appreciated thai if it were possible to impose some form of limit on the physical capacity of a data communication link whilst maintaining compatibility of that link with other links of standard capacity, and without resorting to policing of h-affic at a higher level (for example the ATM level), it would become possible to meet the needs of users and telecommunications suppliers as outlined above.

Accordingly, in one aspect, the invention provides apparatus for controlling data rate over a communication link having a predetermined data rate capacity, the apparatus comprising:

interface means for receiving data, preferably in packets or cells, and for outputting data for transmission over the communication link; and means for signalling to the interface means to inhibit receiving or outputting data to 20 control the data rate transmitted over the communication link substantially to a predetermined allowed data rate less than said predetermined data rate capacity.

With this arrangement, an "artificial" data rate limit is imposed on the link corresponding to the allowed data rate rather than the actual link capacity. As far as any device supplying data to the interface means is concerned, however, this will effectively be a "hard" limit which cannot be circumvented. Thus, the link capacity is regulated at a low level, and complicated policing of the data at a higher level is not needed.

In one preferred arrangemen the signalling means is arranged to inhibit data reception or output at regular intervals (for example every predetermined number of input or output data cells or packets or every predetermined time period). The regular intervals are preferably calculated to have a frequency and preferably duration chosen to achieve a desired allowed data rate. For example, if after every Nth cell, output is inhibited for M cells, the data rate will be reduced to a fraction NI(N+M) of the data rate attainable without such inhibition. The rate without inhibition will normally be approximately equal to the physical capacity of the link, but will typically be marginally higher as the interface means will typically be capable of supplying data at least as fast as the communication link can receive the data, the data rate being conventionally controlled by the link. This arrangement has the benefit of being relatively simple to implement, but precise control of allowed data rate may not be possible, as the interface maximum data rate may not be well defined. In a practical implementation, lack of precision may not be problematic as the invention will typically be used to impose a hard ceiling on the data rate; if a telecommunication supplier provides a line of nominal capacity 75 Mbit/s by effectively halving the data rate over an 0C3 line and in practice the interface can be made to operate at 80 Mbit/s, this will usually be acceptable to both telecommunications supplier and the user, compared to the conventional alternatives.

Alternatively, the signalling means may be arranged to inhibit data flow based on a measure of data rate over the communication link. This has the benefit of allowing more precise control of bandwidth, at the cost of requiring monitoring of actual data rate.

When data transmission is inhibited, particularly where the data is in the form of cells or packets, dummy (null) data or cells are preferably inserted. In the case of an output device arranged to supply a synchronous link, in which cells are packed into synchronous frames, the output device will typically be arranged to insert null cells in the absence of data; generating null cells in such a case need simply comprise delaying supply of data to the output device for a period sufficient for generation of a null cell to commence. In a most preferred arrangement, simple insertion of a delay every N cells will result in insertion of a single null cell every N cells; this enables data rates equal to fractions Nl(W1) of the link data rate to be implemented using only a counter and fixed delay element.

It will be appreciated that, particularly where the data to be. transmitted comprises "bursty" packets of data such as ATM cells, the data rate received by the interface may vary considerably.

Most devices which output such "bursty" data onto a network, particularly a synchronous network such as SONET will incorporate output buffering means, the output buffering means being arranged to receive an inhibit signal from an output device arranged to deliver the data to the network so that a steadier stream of data at a rate with which the network can cope is produced. The invention, as defined in the first aspect, can be integrated into such a device, the buffering 10 means comprising the means for receiving and outputting, and the signalling means being arranged to provide an additional inhibit input to the buffering means.

This feature, together with other preferable and optional features of the first aspect, may be provided in a second aspect, in which the invention provides a device for outputting data, preferably packets or cells, to a communication link, the apparatus comprising:

is buffer means for receiving and storing said data; output means for providing data from the buffer means to the link; means for inhibiting supply of data from the buffer means to the output means to prevent overflow of the output means and to prevent supply of data at a rate substantially greater than a predetermined maximum allowed output rate.

In a further aspect the invention provides apparatus for outputting data, received in packet form, as an output stream to a communication link, the apparatus comprising means for generating null data packets for outputting and means for controlling the insertion of null data packets into the output stream to reduce the effective data-carrying capacity of the communication link substantially to a predetermined value.

The output device preferably comprises an output device of an ATM switch.

The invention extends to corresponding methods of operation.

An embodiment of the invention will now be described, by way of example only, with reference to the accompanying schematic drawing in which:

Figure 1 is a schematic overview of a first embodiment of an ATM switch incorporating the 5 invention; Figure 2 is a schematic timing diagram for explaining the operation of the embodiment of Fig.

Figure 3 is a schematic overview of a second embodiment of an ATM switch incorporating the invention; Figure 4 is a schematic overview of a third embodiment of an ATM switch incorporating the invention.

7he following description is of a simplified switch, concentrating on the inventive features and omitting many conventional details. Details of the switch not described in detail may be implemented in a conventional manner, or may employ advantageous developments described in our concurrently filed applications bearing the references PDG/IK/20137, 20138, 20245, 20246, 20247, the disclosures of which are incorporated herein by reference. Reference may also be made to the ATM forum UNI 3.0 specification, the content of which is incorporated by reference. Further details of ATM and SONET protocols may be found in any of a number of reference books, an example of which is Broadband Communications by Balaji Kumar, published 20 by McGraw-Hill, 1994, the disclosure of which is incorporated herein by reference.

Referring to Figure 1, an ATM switch comprises a plurality of inputs 10 (only three inputs 1 Oa to c are shown, but more or less than three can be provided as well), a switch fabric 12 and a plurality of outputs, each supplying cells for output to an output buffer 14 (only one of which is shown). The output buffer supplies the cells to a physical output device, which packages the cells into a SONET synchronous payload for transmission over an optical fibre. The output buffer is essentially a first in-first out (FIF0) memory, coupled to circuitry for outputting cells sequentially to the physical output device, unless a HALT signal is asserted, and for signalling whether or not any cells remain to be output, via control line 50. Thus, the buffer 14 serves as an interface for receiving data packets from a switch fabric and for outputting the data packets to the physical output device of the switch, the rate of output being controllable by means of an inhibit (HALT) signal.

In the event of the buffer outputting cells faster than the physical output device 16 can handle them, the physical output device is arranged to generate a HALT signal (as will be described further hereinafter) to inhibit buffer output. The physical output device also includes a null cell generator 18 for generating null cells in order to pack the SONET payload to maintain synchronisation in the event of the buffer not having cells for output. If there is not enough data available in the buffer 14, this can be signalled to the output device via control line 50 (this can be signalled by the buffer positively supplying an "empty" signal to the physical output device, or simply by the buffer 14 not supplying a "data available" signal within a predetermined time after a request for data). If the buffer cannot supply data, the null ATM cell generator simply inserts 53 bytes corresponding to a null cell in the SONET payload. Conventional ATM to SONET physical interface devices incorporate such a function, so this will not be described further. The design of the switch thus far may be entirely conventional and is not germane to this invention.

In the embodiment of Fig. 1, in addition to the conventional output interface, a cell counter 20 is provided which counts the number of cells output to the physical device. This is coupled to a comparator 22 which detects when the count reaches a predetermined value, N, and generates a brief pulse to reset the counter. In addition, the output of the comparator is used to delay output of a cell by the buffer; this is achieved by means of the existing HALT input to the buffer, as will be described. The output of the comparator would generally be too short to ensure reliably that output from the buffer is halted for long enough for a null cell to be inserted, so a pulse stretcher 23 (described below) is provided. The stretched signal from stretcher 23 is 0Red with the halt signal from the physical output device in OR gate 24. Thus, every N cells, a halt pulse is generated, the tin-ling of this pulse being arranged so that the buffer output is halted for a sufficient time to ensure that the physical output device detects via control line 50 an absence of data for output and triggers the null cell generator 18 to insert a single null cell in the output. Because the interface is synchronous, a few bytes delay will normally be sufficient to ensure that transmission of a null cell commences, but the stretched pulse may be as long as the time required for transmission of a complete cell.

The operation of pulse stretcher 23 is illustrated by Figure 2, which represents a timing chart (in arbitrary units and not to scale). The upper half of Figure 2 shows the input that comparator 22 delivers to pulse stretcher 23. Comparator 22 produces short pulses every time n cells have been output. The output pulses from the pulse stretcher, depicted in the lower half of this Figure, are longer (stretched), the length of the pulses being chosen to ensure that a null cell will be inserted by the null cell generator. Any suitable conventional pulse stretcher circuit may be employed, for example based on a commercially available timer circuit, the duration of the stretched pulse being chosen based on the output speed of the physical output device. The duration of the pulse may be programmable; this can be used to enable more than one null cell to be inserted, as will be described below.

Thus, the maximum output rate available will be equal to NI(N+1) times the rate of output of the physical output device; this can enable predetermined data rates equal to 1/2, 2/3, 3/4, 4/5 etc. of a standard output rate in a simple fashion (for example, if the physical output is a 155Mbit/s OC-3 connection, approximate data rates of 75 or 100 or about 120 Mbit/s may be provided).

Where greater reduction, or finer control of bandwidth is required, the pulse stretcher can be arranged to halt the output buffer for a time sufficient to ensure that a defined number, M, cells (as opposed to only one cell) are inserted in the output, the output rate then becoming N/(N+n. For example if two null cells are inserted after every cell in an OC-3 connection, a connection of approximately 50Mbit/s is provided. As mentioned above, this can be achieved with the embodiment of Fig. 1 simply by adjusting the length of the pulse output by pulse stretcher 23, 5 which may be programmable.

Thus, with this embodiment, a hard limit can be imposed on the output rate, and this limit may be configurable simply by altering the parameters N and M. This embodiment may be implemented with only slight modification to a conventional cell output interface.

In the above embodiment the output of data from buffer 14 serving as an interface between the switch fabric and the physical output interface is inhibited (even when the physical output device is able to accept the data) to control output rate. An equivalent effect can be achieved by inhibiting input of data to the physical output interface. For example, if the physical output device 16 has an input signifying that data may be input, this may be switched to a false logic level to inhibit input (even when data is in fact available from the buffer), to achieve a similar effect. ' It will be appreciated that, depending on the switch configuration, there may be a plurality of output stages between a switch fabric output port and a physical output, or the switch fabric output may connect directly to the physical output interface; inhibition of data at any convenient interface point between the switch fabric and the physical output of the switch may be employed to control data rate. The interface point may be between physically distinct components, or may be defined logically within a component. References to an %nterface means" above and below are intended to encompass any element, logical or physical, in the output path which is capable of being interrupted to inhibit data output.

Where the physical output device incorporates a (small) buffer, this needs to be taken into account as this will tend to increase the actual data rate if the output buffer can supply data faster than the 1 physical output device normally transmits; in such a case the effective rate will typically be approximately NI(N+n multiplied by the data output rate of output buffer 14 (as opposed to the physical output link speed). Where a large buffer is present in the physical output device, more direct control of null cell insertion is preferable, and the output rate controller is preferably integrated with the physical output device, preferably monitoring actual output data rate or at least deriving a measure of output data rate, for example based on the number of null cells actually inserted (an embodiment incorporating such a feature is described below, with reference to Fig. 4).

The above embodiment halts output based on the number of cells (amount of data) output, to limit actual data output rate. Two alternatives will now be described.

Referring to Figure 3, in an alternative embodiment a clock 52 incorporating a pulse generator is provided to generate a clock signal, for example comprising pulses at predetermined intervals. The timing of these pulses may be similar to the output pulses from the pulse stretcher 23 of the first embodiment as shown in the lower half of Figure 2. As can be seen in Figure 3, the clock 52 delivers the clock signal to the HALT input of buffer 14 via OR gate 24. The frequency at which clock 52 generates pulses can be determined and set according to the output rate required by the user. In this embodiment the output is interrupted at regular intervals, rather than by measuring the number of cells output; this avoids the need to count cells. A pulse stretcher is normally not necessary in this embodiment because a suitable clock 52 can be arranged to generate pulses with an appropriate duty cycle. The operation of the other components (switch, buffer, OR gate and null cell generator) is analogous to the first embodiment. Since data output at the buffer output rate is permitted while the clock signal is low and is inhibited for the duration of the clock signal being high, the effective output rate will be [time clock is low] / [clock total cycle timel [unmodified buffer output rate].

Thus, this embodiment can provide halting of data output at regular, predetermined intervals, to control actual data output rate to a desired rate, lower than the link capacity. The clock rate andlor duty cycle may be programmable, and may be adjustable in response to a measure of actual data rate, as described below.

As mentioned above, in the first embodiment, the output rate may not be precisely controllable if the physical output device includes a significant buffer. This can be alleviated if the rate controller is integrated into the physical output device, providing more direct control of output of cells.

Alternatively, referring now to Figure 4, in another alternative embodiment a rate detector 54 is provided which measures the actual output rate of physical output device 16. This can be achieved, for example, by counting null cells in each SONET packet. Based on the measured output rate from detector 54 and a desired output rate supplied by a store 5 8,, a rate controller 5 6 generates a sequence of pulses which are delivered to the HALT input of buffer 14 via OR gate 24, in a similar manner to the first embodiment.

This embodiment may operate in a generally similar manner to the first embodiment, initially generating a delay of M cells every N cells or in a similar manner to the second embodiment, generating a halt signal at regular intervals. However, because the actual output rate is measured, the controller can adjust the timing of delay pulses to take into account variation in actual output rate (or average over several hundred cells or more) to ensure that a desired average rate is accurately maintained. Thus, this embodiment can provide control based directly on a measure of data rate. The precise algorithm used to control data rate in this embodiment can be tailored to the data rate required. A basic algorithm is outlined below in pseudo- code:

Initially:

Regularly:

Set initial halt pulse timing based on desired output rate.

Generate halt pulses according to initial timing.

Every x cells, obtain measure of actual data rate and compare to desired rate.

11 - As necessary, based on comparison:

Adjust initial timing based on measured d&a rate. Insert additional delaypulses based on measured data rate, or Inhibit or shorten delaypulse based on measured data rate.

Thus, the initially set timing can be adjusted to compensate for long term drifts in output rate. Additionally, to correct the drifts over a shorter timescale, additional delay pulses can be inserted or certain of the regular pulses can be lengthened (to slow down the output rate), or certain of the regular pulses may be shortened or omitted (to increase the output rate).

Although described in the context of an ATM switch, the invention can be extended to other data 10 switches having similar architecture. It should be noted that where data is not transmitted in discrete packets, insertion of null data may necessitate including information enabling the "real" data to be distinguished from the null data; where data is sent in discrete packets, it will normally be straightforward to flag packets as containing null information which can be discarded. Each feature disclosed herein may be independently provided unless otherwise stated.

Claims

!CLAIMS:

1. Apparatus for controlling data rate over a communication link having a predetermined data rate capacity, the apparatus comprising: interface means for receiving data and for outputting data for transmission over the communication link; and means for signalling to the interface means to inhibit receiving or outputting data to control the data rate transmitted over the communication link substantially to a predetermined allowed data rate less than said predetermined data rate capacity, said signalling being controlled according to a predetermined timing or in dependence on a measure of the amount of data output or based on a measure of data rate.

2.

3.

Apparatus for outputting data to a communication link, the apparatus comprising: buffer means for receiving and storing the data; output means for providing data from the buffer means to the link; means for inhibiting supply of data from the buffer means to the output means to prevent overflow of the output means and to prevent supply of data at a rate substantially greater than a predetermined maximum allowed output rate, said inhibiting being controlled according to a predetermined timing or in dependence on a measure of the amount of data output or based on a measure of data rate.

Apparatus according to Claim 1 or Claim 2, arranged to receive data in the form of cells or packets.

4. Apparatus according to Claim 3 arranged to receive ATM cells.

5. Apparatus according to any preceding claim, wherein the communication link is a synchronous link.

6. Apparatus according to Claim 5, wherein the link is a SONET link.

7. Apparatus according to any preceding claim arranged to inhibit data output at repeated intervals.

8. Apparatus according to Claim 7, wherein the intervals are based on the number of data cells output.

9. Apparatus according to any preceding claim arranged to inhibit data output based on a measure of the data transmission rate.

10. Apparatus according to Claim 3 or Claim 4, or any claim as dependent thereon, arranged to insert empty cells or packets in the output data transmitted over the communication link.

11. Apparatus according to Claim 10 arranged to insert M empty cells for every N data cells transmitted, where N and M are predetermined irambers, preferably configurable.

is

12. A method of controlling data rate over a communication link having a predetermined data rate capacity, the method comprising: receiving data and outputting data for transmission over the communication link; and inhibiting receiving or outputting data to control the data rate transmitted over the communication link substantially to a predetermined allowed data rate less than said predetermined data rate capacity.

13. A method according to Claim 12 including inserting null data cells in the output.

14. Apparatus for outputting data, received in packet form, as an output stream to a communication link, the apparatus comprising means for generating null data packets for outputting and means for controlling the insertion of null data packets into the output stream to reduce the effective data-carrying capacity of the communication link substantially to a predetermined value.

15. Apparatus substantially as herein described or as illustrated.

16. A method substantially as herein described.