ATE293851T1 - Verfahren zur bestimmung eines reihenfolges von verzögerungszellen in einer n-zellenkette - Google Patents

Verfahren zur bestimmung eines reihenfolges von verzögerungszellen in einer n-zellenkette

Info

Publication number
ATE293851T1
ATE293851T1 AT01403055T AT01403055T ATE293851T1 AT E293851 T1 ATE293851 T1 AT E293851T1 AT 01403055 T AT01403055 T AT 01403055T AT 01403055 T AT01403055 T AT 01403055T AT E293851 T1 ATE293851 T1 AT E293851T1
Authority
AT
Austria
Prior art keywords
value
error
delay
loop
cell
Prior art date
Application number
AT01403055T
Other languages
English (en)
Inventor
Jean-Marie Boudry
Original Assignee
Bull Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull Sa filed Critical Bull Sa
Application granted granted Critical
Publication of ATE293851T1 publication Critical patent/ATE293851T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

Landscapes

  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Circuits Of Receivers In General (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
  • Measuring Or Testing Involving Enzymes Or Micro-Organisms (AREA)
AT01403055T 2000-12-07 2001-11-29 Verfahren zur bestimmung eines reihenfolges von verzögerungszellen in einer n-zellenkette ATE293851T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0015856A FR2817981B1 (fr) 2000-12-07 2000-12-07 Circuit multiplieur de fronts

Publications (1)

Publication Number Publication Date
ATE293851T1 true ATE293851T1 (de) 2005-05-15

Family

ID=8857332

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01403055T ATE293851T1 (de) 2000-12-07 2001-11-29 Verfahren zur bestimmung eines reihenfolges von verzögerungszellen in einer n-zellenkette

Country Status (6)

Country Link
US (1) US6636088B2 (de)
EP (1) EP1213839B1 (de)
JP (1) JP3676730B2 (de)
AT (1) ATE293851T1 (de)
DE (1) DE60110194T2 (de)
FR (1) FR2817981B1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7202719B2 (en) * 2004-09-30 2007-04-10 Motorola, Inc. Method and apparatus for frequency synthesis

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
US5812832A (en) * 1993-01-29 1998-09-22 Advanced Micro Devices, Inc. Digital clock waveform generator and method for generating a clock signal
US5552726A (en) * 1993-05-05 1996-09-03 Texas Instruments Incorporated High resolution digital phase locked loop with automatic recovery logic
US5422835A (en) * 1993-07-28 1995-06-06 International Business Machines Corporation Digital clock signal multiplier circuit
JP3319340B2 (ja) * 1997-05-30 2002-08-26 日本電気株式会社 半導体回路装置
US6037812A (en) * 1998-05-18 2000-03-14 National Semiconductor Corporation Delay locked loop (DLL) based clock synthesis

Also Published As

Publication number Publication date
US6636088B2 (en) 2003-10-21
JP3676730B2 (ja) 2005-07-27
EP1213839B1 (de) 2005-04-20
DE60110194D1 (de) 2005-05-25
US20020113630A1 (en) 2002-08-22
EP1213839A1 (de) 2002-06-12
FR2817981B1 (fr) 2003-02-14
JP2002208846A (ja) 2002-07-26
DE60110194T2 (de) 2006-03-09
FR2817981A1 (fr) 2002-06-14

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