ATE289098T1 - Multicomputersystem mit konfigurierbaren schnittstellen für flexible systemkonfigurationen - Google Patents
Multicomputersystem mit konfigurierbaren schnittstellen für flexible systemkonfigurationenInfo
- Publication number
- ATE289098T1 ATE289098T1 AT02025687T AT02025687T ATE289098T1 AT E289098 T1 ATE289098 T1 AT E289098T1 AT 02025687 T AT02025687 T AT 02025687T AT 02025687 T AT02025687 T AT 02025687T AT E289098 T1 ATE289098 T1 AT E289098T1
- Authority
- AT
- Austria
- Prior art keywords
- systems
- memories
- multicomputer
- flexible
- interface circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US33178901P | 2001-11-20 | 2001-11-20 | |
US34471301P | 2001-12-24 | 2001-12-24 | |
US34871702P | 2002-01-14 | 2002-01-14 | |
US34877702P | 2002-01-14 | 2002-01-14 | |
US38074002P | 2002-05-15 | 2002-05-15 | |
US10/270,014 US7394823B2 (en) | 2001-11-20 | 2002-10-11 | System having configurable interfaces for flexible system configurations |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE289098T1 true ATE289098T1 (de) | 2005-02-15 |
Family
ID=27559480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT02025687T ATE289098T1 (de) | 2001-11-20 | 2002-11-20 | Multicomputersystem mit konfigurierbaren schnittstellen für flexible systemkonfigurationen |
Country Status (4)
Country | Link |
---|---|
US (2) | US7394823B2 (de) |
EP (1) | EP1313029B1 (de) |
AT (1) | ATE289098T1 (de) |
DE (1) | DE60202926T2 (de) |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020131412A1 (en) * | 2001-01-12 | 2002-09-19 | Dipak Shah | Switch fabric with efficient spatial multicast |
US6965602B2 (en) * | 2001-01-12 | 2005-11-15 | Peta Switch Solutions, Inc. | Switch fabric capable of aggregating multiple chips and links for high bandwidth operation |
US20030021230A1 (en) * | 2001-03-09 | 2003-01-30 | Petaswitch Solutions, Inc. | Switch fabric with bandwidth efficient flow control |
US7206879B2 (en) * | 2001-11-20 | 2007-04-17 | Broadcom Corporation | Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems |
US7352748B1 (en) * | 2002-03-28 | 2008-04-01 | Redback Networks Inc. | Updating of routing data in a network element |
US20040213219A1 (en) * | 2002-07-03 | 2004-10-28 | Sridhar Lakshmanamurthy | Method and apparatus to handle the flow control in a cascaded configuration |
US7386768B2 (en) * | 2003-06-05 | 2008-06-10 | Intel Corporation | Memory channel with bit lane fail-over |
WO2005008998A1 (en) * | 2003-07-03 | 2005-01-27 | Sinett Corporation | Initialization vector generation algorithm and hardware architecture |
WO2005008980A1 (en) * | 2003-07-03 | 2005-01-27 | Sinett Corporation | Unified wired and wireless switch architecture |
WO2005008982A1 (en) * | 2003-07-03 | 2005-01-27 | Sinett Corporation | Method of stacking multiple devices to create the equivalent of a single device with a larger port count |
US7656898B2 (en) * | 2003-09-18 | 2010-02-02 | Brocade Communications Systems, Inc. | Virtual channel remapping |
US6981074B2 (en) * | 2003-10-14 | 2005-12-27 | Broadcom Corporation | Descriptor-based load balancing |
US7685434B2 (en) | 2004-03-02 | 2010-03-23 | Advanced Micro Devices, Inc. | Two parallel engines for high speed transmit IPsec processing |
US20060045009A1 (en) * | 2004-08-30 | 2006-03-02 | Ken Madison | Device and method for managing oversubsription in a network |
TWI321414B (en) | 2004-10-15 | 2010-03-01 | Sony Computer Entertainment Inc | Methods and apparatus for supporting multiple configurations in a multi-processor system |
TW200627185A (en) * | 2005-01-18 | 2006-08-01 | Portwell Inc | Single-board computer motherboard for industrial computer |
US7739424B2 (en) * | 2005-04-18 | 2010-06-15 | Integrated Device Technology, Inc. | Packet processing switch and methods of operation thereof |
US7480747B2 (en) * | 2005-06-08 | 2009-01-20 | Intel Corporation | Method and apparatus to reduce latency and improve throughput of input/output data in a processor |
US20070050524A1 (en) * | 2005-08-26 | 2007-03-01 | Intel Corporation | Configurable notification generation |
US7805560B2 (en) * | 2005-08-31 | 2010-09-28 | Ati Technologies Inc. | Methods and apparatus for translating messages in a computing system |
US20070073966A1 (en) * | 2005-09-23 | 2007-03-29 | Corbin John R | Network processor-based storage controller, compute element and method of using same |
US20070076685A1 (en) * | 2005-09-30 | 2007-04-05 | Pak-Lung Seto | Programmable routing for frame-packet based frame processing |
US7725573B2 (en) * | 2005-11-29 | 2010-05-25 | Intel Corporation | Methods and apparatus for supporting agile run-time network systems via identification and execution of most efficient application code in view of changing network traffic conditions |
US7817652B1 (en) * | 2006-05-12 | 2010-10-19 | Integrated Device Technology, Inc. | System and method of constructing data packets in a packet switch |
US7747904B1 (en) | 2006-05-12 | 2010-06-29 | Integrated Device Technology, Inc. | Error management system and method for a packet switch |
US7706387B1 (en) | 2006-05-31 | 2010-04-27 | Integrated Device Technology, Inc. | System and method for round robin arbitration |
GB2444745B (en) * | 2006-12-13 | 2011-08-24 | Advanced Risc Mach Ltd | Data transfer between a master and slave |
US8000229B2 (en) * | 2007-02-07 | 2011-08-16 | Lightfleet Corporation | All-to-all interconnect fabric generated monotonically increasing identifier |
US8345702B2 (en) | 2007-02-07 | 2013-01-01 | Marvell World Trade Ltd. | Method and apparatus for flexible interface bypass options in switches |
US8200992B2 (en) | 2007-09-24 | 2012-06-12 | Cognitive Electronics, Inc. | Parallel processing computer systems with reduced power consumption and methods for providing the same |
US8411807B1 (en) | 2008-09-02 | 2013-04-02 | Cisco Technology, Inc. | Mid-packet clear channel assessment |
WO2010090838A2 (en) * | 2009-01-20 | 2010-08-12 | The Regents Of The University Of California | Reducing cabling complexity in large-scale networks |
US8209597B2 (en) | 2009-03-23 | 2012-06-26 | Cognitive Electronics, Inc. | System and method for achieving improved accuracy from efficient computer architectures |
TW201038036A (en) * | 2009-04-03 | 2010-10-16 | Ra Link Technology Corp | Method for generating hash keys and apparatus for using the same |
US8392661B1 (en) * | 2009-09-21 | 2013-03-05 | Tilera Corporation | Managing cache coherence |
BRPI1004997A2 (pt) * | 2009-11-11 | 2013-02-26 | Seiko Epson Corp | dispositivo eletrânico e mÉtodo de controle do mesmo |
US9069489B1 (en) | 2010-03-29 | 2015-06-30 | Marvell Israel (M.I.S.L) Ltd. | Dynamic random access memory front end |
US20110228674A1 (en) * | 2010-03-18 | 2011-09-22 | Alon Pais | Packet processing optimization |
IL211490A (en) * | 2010-03-02 | 2016-09-29 | Marvell Israel(M I S L ) Ltd | Early next packets of information |
US8327047B2 (en) | 2010-03-18 | 2012-12-04 | Marvell World Trade Ltd. | Buffer manager and methods for managing memory |
US8788761B2 (en) * | 2010-09-24 | 2014-07-22 | Nvidia Corporation | System and method for explicitly managing cache coherence |
US9098203B1 (en) | 2011-03-01 | 2015-08-04 | Marvell Israel (M.I.S.L) Ltd. | Multi-input memory command prioritization |
US9042383B2 (en) * | 2011-06-30 | 2015-05-26 | Broadcom Corporation | Universal network interface controller |
US9141131B2 (en) | 2011-08-26 | 2015-09-22 | Cognitive Electronics, Inc. | Methods and systems for performing exponentiation in a parallel processing environment |
US9253121B2 (en) | 2012-12-31 | 2016-02-02 | Broadcom Corporation | Universal network interface controller |
US9063754B2 (en) | 2013-03-15 | 2015-06-23 | Cognitive Electronics, Inc. | Profiling and optimization of program code/application |
CN103294612B (zh) * | 2013-03-22 | 2014-08-13 | 浪潮电子信息产业股份有限公司 | 在多级缓存一致性域系统局部域构造Share-F状态的方法 |
FR3026869B1 (fr) * | 2014-10-07 | 2016-10-28 | Sagem Defense Securite | Systeme embarque sur puce a haute surete de fonctionnement |
US10095631B2 (en) * | 2015-12-10 | 2018-10-09 | Arm Limited | System address map for hashing within a chip and between chips |
US10402326B1 (en) | 2016-04-26 | 2019-09-03 | Apple Inc. | Accessing memories in coherent and non-coherent domains in a computing system |
Family Cites Families (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4788679A (en) * | 1986-09-02 | 1988-11-29 | Nippon Telegraph And Telephone Corporation | Packet switch with variable data transfer rate links |
CH670715A5 (de) | 1986-10-03 | 1989-06-30 | Bbc Brown Boveri & Cie | |
US5765011A (en) * | 1990-11-13 | 1998-06-09 | International Business Machines Corporation | Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams |
US5963745A (en) * | 1990-11-13 | 1999-10-05 | International Business Machines Corporation | APAP I/O programmable router |
US5623628A (en) * | 1994-03-02 | 1997-04-22 | Intel Corporation | Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue |
US5634004A (en) * | 1994-05-16 | 1997-05-27 | Network Programs, Inc. | Directly programmable distribution element |
DE59507871D1 (de) * | 1994-07-12 | 2000-04-06 | Ascom Ag | Vorrichtung zur Vermittlung in digitalen Datennetzen für asynchronen Transfermodus |
DE69616402T2 (de) * | 1995-03-31 | 2002-07-18 | Sun Microsystems Inc | Schnelle Zweitor-Cachesteuerungsschaltung für Datenprozessoren in einem paketvermittelten cachekohärenten Multiprozessorsystem |
US5805920A (en) | 1995-11-13 | 1998-09-08 | Tandem Computers Incorporated | Direct bulk data transfers |
US5710907A (en) * | 1995-12-22 | 1998-01-20 | Sun Microsystems, Inc. | Hybrid NUMA COMA caching system and methods for selecting between the caching modes |
US5689500A (en) * | 1996-01-16 | 1997-11-18 | Lucent Technologies, Inc. | Multistage network having multicast routing congestion feedback |
US5887138A (en) * | 1996-07-01 | 1999-03-23 | Sun Microsystems, Inc. | Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes |
US5878268A (en) * | 1996-07-01 | 1999-03-02 | Sun Microsystems, Inc. | Multiprocessing system configured to store coherency state within multiple subnodes of a processing node |
US5813029A (en) * | 1996-07-09 | 1998-09-22 | Micron Electronics, Inc. | Upgradeable cache circuit using high speed multiplexer |
US5961623A (en) * | 1996-08-29 | 1999-10-05 | Apple Computer, Inc. | Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system |
WO1998015155A1 (de) | 1996-09-30 | 1998-04-09 | Siemens Aktiengesellschaft | Verfahren zur mehrpunktverbindung in einem atm-übertragungssystem mit verbindungsindividuellen warteschlangen |
JPH10154100A (ja) * | 1996-11-25 | 1998-06-09 | Canon Inc | 情報処理システム及び装置及びその制御方法 |
JP3904282B2 (ja) * | 1997-03-31 | 2007-04-11 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US6298370B1 (en) * | 1997-04-04 | 2001-10-02 | Texas Instruments Incorporated | Computer operating process allocating tasks between first and second processors at run time based upon current processor load |
US6105119A (en) * | 1997-04-04 | 2000-08-15 | Texas Instruments Incorporated | Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems |
US6182201B1 (en) * | 1997-04-14 | 2001-01-30 | International Business Machines Corporation | Demand-based issuance of cache operations to a system bus |
FR2762418B1 (fr) * | 1997-04-17 | 1999-06-11 | Alsthom Cge Alcatel | Procede de gestion d'une memoire partagee |
JP3524337B2 (ja) | 1997-07-25 | 2004-05-10 | キヤノン株式会社 | バス管理装置及びそれを有する複合機器の制御装置 |
US6128728A (en) * | 1997-08-01 | 2000-10-03 | Micron Technology, Inc. | Virtual shadow registers and virtual register windows |
US6209065B1 (en) * | 1997-10-24 | 2001-03-27 | Compaq Computer Corporation | Mechanism for optimizing generation of commit-signals in a distributed shared-memory system |
US6085294A (en) * | 1997-10-24 | 2000-07-04 | Compaq Computer Corporation | Distributed data dependency stall mechanism |
US6108752A (en) * | 1997-10-24 | 2000-08-22 | Compaq Computer Corporation | Method and apparatus for delaying victim writes in a switch-based multi-processor system to maintain data coherency |
US6101420A (en) * | 1997-10-24 | 2000-08-08 | Compaq Computer Corporation | Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories |
US6032228A (en) * | 1997-11-26 | 2000-02-29 | International Business Machines Corporation | Flexible cache-coherency mechanism |
FR2771573B1 (fr) | 1997-11-27 | 2001-10-19 | Alsthom Cge Alkatel | Element de commutation de paquets a memoires tampons |
US6141733A (en) | 1998-02-17 | 2000-10-31 | International Business Machines Corporation | Cache coherency protocol with independent implementation of optimized cache operations |
JP3563257B2 (ja) | 1998-02-20 | 2004-09-08 | Necエレクトロニクス株式会社 | Atmスイッチ回路 |
US6289419B1 (en) | 1998-03-06 | 2001-09-11 | Sharp Kabushiki Kaisha | Consistency control device merging updated memory blocks |
US6070215A (en) * | 1998-03-13 | 2000-05-30 | Compaq Computer Corporation | Computer system with improved transition to low power operation |
GB9806184D0 (en) | 1998-03-23 | 1998-05-20 | Sgs Thomson Microelectronics | A cache coherency mechanism |
US6185520B1 (en) * | 1998-05-22 | 2001-02-06 | 3Com Corporation | Method and system for bus switching data transfers |
US6195739B1 (en) * | 1998-06-29 | 2001-02-27 | Cisco Technology, Inc. | Method and apparatus for passing data among processor complex stages of a pipelined processing engine |
US6266731B1 (en) * | 1998-09-03 | 2001-07-24 | Compaq Computer Corporation | High speed peripheral interconnect apparatus, method and system |
US6338122B1 (en) * | 1998-12-15 | 2002-01-08 | International Business Machines Corporation | Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node |
US6631401B1 (en) | 1998-12-21 | 2003-10-07 | Advanced Micro Devices, Inc. | Flexible probe/probe response routing for maintaining coherency |
US6714994B1 (en) * | 1998-12-23 | 2004-03-30 | Advanced Micro Devices, Inc. | Host bridge translating non-coherent packets from non-coherent link to coherent packets on conherent link and vice versa |
US6425060B1 (en) | 1999-01-05 | 2002-07-23 | International Business Machines Corporation | Circuit arrangement and method with state-based transaction scheduling |
JP3636986B2 (ja) * | 2000-12-06 | 2005-04-06 | 松下電器産業株式会社 | 半導体集積回路 |
US20020103921A1 (en) * | 2001-01-31 | 2002-08-01 | Shekar Nair | Method and system for routing broadband internet traffic |
US20040062261A1 (en) * | 2001-02-07 | 2004-04-01 | Rami Zecharia | Multi-service segmentation and reassembly device having integrated scheduler and advanced multi-timing wheel shaper |
US6901052B2 (en) * | 2001-05-04 | 2005-05-31 | Slt Logic Llc | System and method for policing multiple data flows and multi-protocol data flows |
US6615322B2 (en) * | 2001-06-21 | 2003-09-02 | International Business Machines Corporation | Two-stage request protocol for accessing remote memory data in a NUMA data processing system |
-
2002
- 2002-10-11 US US10/270,014 patent/US7394823B2/en active Active
- 2002-11-20 EP EP02025687A patent/EP1313029B1/de not_active Expired - Lifetime
- 2002-11-20 DE DE60202926T patent/DE60202926T2/de not_active Expired - Lifetime
- 2002-11-20 AT AT02025687T patent/ATE289098T1/de not_active IP Right Cessation
-
2008
- 2008-05-30 US US12/130,044 patent/US20080228871A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US7394823B2 (en) | 2008-07-01 |
EP1313029A1 (de) | 2003-05-21 |
EP1313029B1 (de) | 2005-02-09 |
US20080228871A1 (en) | 2008-09-18 |
US20030097467A1 (en) | 2003-05-22 |
DE60202926T2 (de) | 2006-04-13 |
DE60202926D1 (de) | 2005-03-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE289098T1 (de) | Multicomputersystem mit konfigurierbaren schnittstellen für flexible systemkonfigurationen | |
ATE508412T1 (de) | Kohärenzsteuerungsvorrichtung für eine mehrprozessorvorrichtung, modul und multimodularchitektur-mehrprozessorvorrichtung mit einer derartigen steuervorrichtung | |
ATE309574T1 (de) | System mit schnittstellen, einem schalter und einer speicherbrücke mit cc-numa (cache-coherent non-uniform memory access) | |
DK220883A (da) | Multiprocessordatamatsystem | |
DE69021429T2 (de) | Speicherzugriffssteuerschaltung für Grafik-Steuergerät. | |
DE59406518D1 (de) | Schaltungsanordnung für sicherheitskritische regelungssysteme | |
DE69231452T2 (de) | Fehlertolerantes Rechnersystem mit Verarbeitungseinheiten die je mindestens drei Rechnereinheiten haben | |
ATE292305T1 (de) | System mit schnittstellen und einem schalter für die trennung von kohärentem und nichtkohärentem datenpaketverkehr | |
DE69233655D1 (de) | Mikroprozessorarchitektur mit der Möglichkeit zur Unterstützung mehrerer verschiedenartiger Prozessoren | |
ES2065035T3 (es) | Procedimiento y dispositivo de transaccion entre un primer y por lo menos un segundo soporte de datos y soporte para este fin. | |
ATE259081T1 (de) | Mehrprozessorsystem prüfungsschaltung | |
ATE192874T1 (de) | Speichervorrichtung und datenverarbeitungssystem mit einer solchen speichervorrichtung | |
KR910010336A (ko) | 프로세서 및 메모리의 크로스바 링크를 갖는 멀티프로세서 시스템 및 이의 동작 방법 | |
DE69128755T2 (de) | Systemzustandssteuergerät für elektronische Bildverarbeitungssysteme | |
DE19983443T1 (de) | Außer-der-Reihe-Snooping für Multiprozessor-Computersysteme | |
DE69129101T2 (de) | Steuerungsanordnung für Cachespeichereinheit | |
DE69817298D1 (de) | Vorrichtung zur Kommunikation zwischen Informationsverarbeitungseinheiten und mit einem gemeinsamen Bus verbundenenen Prozessoren | |
DE60034065D1 (de) | Informationsverarbeitungseinheit | |
ES2085429T3 (es) | Sistema de comunicacion entre un dispositivo calculador y dispositivos perifericos. | |
DE69832007D1 (de) | Steuerschaltung für Computerspeicher | |
KR20150067433A (ko) | L2 캐시 특성을 조절할 수 있는 멀티-코어 cpu 시스템, 이의 동작 방법, 및 이를 포함하는 장치들 | |
DE69118781D1 (de) | Übertragungssteuerungssystem für einen Rechner und Peripheriegeräte | |
JP2001318901A (ja) | 2重化マルチプロセッサ方式 | |
ATE261141T1 (de) | Programmgesteuerte einrichtung mit nachlademöglichkeit für und umschaltemöglichkeit auf zweites betriebssystem ohne programmunterbrechung | |
KR960025112A (ko) | 다수의 프로세서가 하나의 캐쉬 메모리를 공유하는 시스템 장치 및 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |