ATE257990T1 - Serieller frequenzumsetzer mit tolerierung von jitter an der nutzlast - Google Patents
Serieller frequenzumsetzer mit tolerierung von jitter an der nutzlastInfo
- Publication number
- ATE257990T1 ATE257990T1 AT93115140T AT93115140T ATE257990T1 AT E257990 T1 ATE257990 T1 AT E257990T1 AT 93115140 T AT93115140 T AT 93115140T AT 93115140 T AT93115140 T AT 93115140T AT E257990 T1 ATE257990 T1 AT E257990T1
- Authority
- AT
- Austria
- Prior art keywords
- flowrate
- serial
- high data
- stream
- rate
- Prior art date
Links
- 238000006243 chemical reaction Methods 0.000 abstract 3
- RGNPBRKPHBKNKX-UHFFFAOYSA-N hexaflumuron Chemical compound C1=C(Cl)C(OC(F)(F)C(F)F)=C(Cl)C=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F RGNPBRKPHBKNKX-UHFFFAOYSA-N 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/12—Arrangements providing for calling or supervisory signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0057—Operations, administration and maintenance [OAM]
- H04J2203/0058—Network management, e.g. Intelligent nets
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Dc Digital Transmission (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Optical Communication System (AREA)
- Television Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/962,319 US5425062A (en) | 1992-10-16 | 1992-10-16 | Serial rate conversion circuit with jitter tolerant payload |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE257990T1 true ATE257990T1 (de) | 2004-01-15 |
Family
ID=25505702
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT93115140T ATE257990T1 (de) | 1992-10-16 | 1993-09-21 | Serieller frequenzumsetzer mit tolerierung von jitter an der nutzlast |
Country Status (5)
Country | Link |
---|---|
US (1) | US5425062A (de) |
EP (1) | EP0592842B1 (de) |
AT (1) | ATE257990T1 (de) |
DE (1) | DE69333381T2 (de) |
ES (1) | ES2210233T3 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5692159A (en) * | 1995-05-19 | 1997-11-25 | Digital Equipment Corporation | Configurable digital signal interface using field programmable gate array to reformat data |
US6198720B1 (en) * | 1996-12-26 | 2001-03-06 | Alcatel Usa Sourcing, L.P. | Distributed digital cross-connect system and method |
KR100251736B1 (ko) * | 1997-12-29 | 2000-04-15 | 윤종용 | 직렬 데이터의 전송속도 변환 장치 |
US6928573B2 (en) * | 2001-11-20 | 2005-08-09 | Broadcom Corporation | Communication clocking conversion techniques |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4229815A (en) * | 1978-11-20 | 1980-10-21 | Bell Telephone Laboratories, Incorporated | Full duplex bit synchronous data rate buffer |
US4259738A (en) * | 1979-05-18 | 1981-03-31 | Raytheon Company | Multiplexer system providing improved bit count integrity |
US4839893A (en) * | 1987-10-05 | 1989-06-13 | Dallas Semiconductor Corporation | Telecommunications FIFO |
-
1992
- 1992-10-16 US US07/962,319 patent/US5425062A/en not_active Expired - Lifetime
-
1993
- 1993-09-21 ES ES93115140T patent/ES2210233T3/es not_active Expired - Lifetime
- 1993-09-21 EP EP93115140A patent/EP0592842B1/de not_active Expired - Lifetime
- 1993-09-21 DE DE69333381T patent/DE69333381T2/de not_active Expired - Fee Related
- 1993-09-21 AT AT93115140T patent/ATE257990T1/de not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE69333381T2 (de) | 2004-10-14 |
DE69333381D1 (de) | 2004-02-19 |
EP0592842A2 (de) | 1994-04-20 |
EP0592842B1 (de) | 2004-01-14 |
EP0592842A3 (en) | 1996-03-06 |
US5425062A (en) | 1995-06-13 |
ES2210233T3 (es) | 2004-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0445574A3 (en) | Digital clock buffer circuit providing controllable delay | |
DE69328521D1 (de) | Inkrementaler Phasenglättungsdesynchronisierer und Rechenanordnung | |
CA2179235A1 (en) | Built-in test scheme for a jitter tolerance test of a clock and data recovery unit | |
CA2088156A1 (en) | Method and means for transferring a data payload from a first sonet signal to a sonet signal of different frequency | |
MY105780A (en) | Digital transmission system, transmitter and receiver for use in the transmission sytstem, and record carrier obtained by means of the treansmitter in the form of a recording device | |
AU8353491A (en) | Justification decision circuit for an arrangement for bit rate adjustment | |
EP1043721A3 (de) | Verfahren zur Aufnahme von digitalen Daten | |
JPH04227142A (ja) | 2つのディジタル信号のビット速度調整用回路配置 | |
ES2146576T3 (es) | Disposicion de bucle con enganche de pase. | |
DE69333381D1 (de) | Serieller Frequenzumsetzer mit Tolerierung von Jitter an der Nutzlast | |
CA2105659A1 (en) | Optical clock extraction | |
GB2204467A (en) | Method and apparatus for generating a data recovery window | |
ES2117040T3 (es) | Dispositivo de sincronizacion para equipamiento de terminal de una red de telecomunicaciones digital con transferencia en modo asincrono. | |
CA2161609A1 (en) | Digital signal recording apparatus | |
JPS57208752A (en) | Sub-signal transmitting system | |
GR3033221T3 (en) | Method and arrangement for recovering plesiochrone signals transmitted in tributaries. | |
DE69721183D1 (de) | Digitalsignalwiedergabe | |
ATE120061T1 (de) | Synchronisiereinrichtung für ein digitalsignal. | |
AU4611789A (en) | Jitter reduction circuit in a demultiplexer | |
EP0559957A3 (de) | ||
CA2063000A1 (en) | Method and circuit for demultiplexing digital signals capable of absorbing destuffing jitter | |
SU1392619A1 (ru) | Дельта-декодер | |
JPS6471345A (en) | Data transmitter | |
GR3007226T3 (de) | ||
JPS573458A (en) | Carrier pickup circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |