ATE233414T1 - Prozessor und verfahren zur spekulativen ausführung von bedingten verzweigungsbefehlen unter verwendung einer von mehreren verzweigungsvorhersageverfahren - Google Patents

Prozessor und verfahren zur spekulativen ausführung von bedingten verzweigungsbefehlen unter verwendung einer von mehreren verzweigungsvorhersageverfahren

Info

Publication number
ATE233414T1
ATE233414T1 AT97302877T AT97302877T ATE233414T1 AT E233414 T1 ATE233414 T1 AT E233414T1 AT 97302877 T AT97302877 T AT 97302877T AT 97302877 T AT97302877 T AT 97302877T AT E233414 T1 ATE233414 T1 AT E233414T1
Authority
AT
Austria
Prior art keywords
branch
prediction
branch prediction
processor
instructions
Prior art date
Application number
AT97302877T
Other languages
English (en)
Inventor
Soummya Mallick
Albert John Loper
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE233414T1 publication Critical patent/ATE233414T1/de

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3848—Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Eye Examination Apparatus (AREA)
  • Image Processing (AREA)
AT97302877T 1996-04-29 1997-04-25 Prozessor und verfahren zur spekulativen ausführung von bedingten verzweigungsbefehlen unter verwendung einer von mehreren verzweigungsvorhersageverfahren ATE233414T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/639,577 US5752014A (en) 1996-04-29 1996-04-29 Automatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction

Publications (1)

Publication Number Publication Date
ATE233414T1 true ATE233414T1 (de) 2003-03-15

Family

ID=24564688

Family Applications (1)

Application Number Title Priority Date Filing Date
AT97302877T ATE233414T1 (de) 1996-04-29 1997-04-25 Prozessor und verfahren zur spekulativen ausführung von bedingten verzweigungsbefehlen unter verwendung einer von mehreren verzweigungsvorhersageverfahren

Country Status (7)

Country Link
US (1) US5752014A (de)
EP (1) EP0805390B1 (de)
JP (1) JP3397081B2 (de)
KR (1) KR100270003B1 (de)
AT (1) ATE233414T1 (de)
DE (1) DE69719235T2 (de)
TW (1) TW344060B (de)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6151672A (en) * 1998-02-23 2000-11-21 Hewlett-Packard Company Methods and apparatus for reducing interference in a branch history table of a microprocessor
US6374349B2 (en) * 1998-03-19 2002-04-16 Mcfarling Scott Branch predictor with serially connected predictor stages for improving branch prediction accuracy
US6115809A (en) * 1998-04-30 2000-09-05 Hewlett-Packard Company Compiling strong and weak branching behavior instruction blocks to separate caches for dynamic and static prediction
US6081887A (en) * 1998-05-13 2000-06-27 Compaq Computer Corporation System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction
US6247146B1 (en) * 1998-08-17 2001-06-12 Advanced Micro Devices, Inc. Method for verifying branch trace history buffer information
US6189091B1 (en) 1998-12-02 2001-02-13 Ip First, L.L.C. Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection
JP3565314B2 (ja) 1998-12-17 2004-09-15 富士通株式会社 分岐命令実行制御装置
US6338133B1 (en) 1999-03-12 2002-01-08 International Business Machines Corporation Measured, allocation of speculative branch instructions to processor execution units
US6499101B1 (en) 1999-03-18 2002-12-24 I.P. First L.L.C. Static branch prediction mechanism for conditional branch instructions
US6546481B1 (en) 1999-11-05 2003-04-08 Ip - First Llc Split history tables for branch prediction
JP2001243070A (ja) * 2000-02-29 2001-09-07 Toshiba Corp プロセッサ及び分岐予測方法並びにコンパイル方法
US6766442B1 (en) 2000-03-30 2004-07-20 International Business Machines Corporation Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value
US6658558B1 (en) * 2000-03-30 2003-12-02 International Business Machines Corporation Branch prediction circuit selector with instruction context related condition type determining
US6678820B1 (en) 2000-03-30 2004-01-13 International Business Machines Corporation Processor and method for separately predicting conditional branches dependent on lock acquisition
US6859875B1 (en) * 2000-06-12 2005-02-22 Freescale Semiconductor, Inc. Processor having selective branch prediction
US7404070B1 (en) * 2000-11-28 2008-07-22 Hewlett-Packard Development Company, L.P. Branch prediction combining static and dynamic prediction techniques
US20050273559A1 (en) * 2004-05-19 2005-12-08 Aris Aristodemou Microprocessor architecture including unified cache debug unit
US7587580B2 (en) 2005-02-03 2009-09-08 Qualcomm Corporated Power efficient instruction prefetch mechanism
US20060190710A1 (en) * 2005-02-24 2006-08-24 Bohuslav Rychlik Suppressing update of a branch history register by loop-ending branches
US7971042B2 (en) * 2005-09-28 2011-06-28 Synopsys, Inc. Microprocessor system and method for instruction-initiated recording and execution of instruction sequences in a dynamically decoupleable extended instruction pipeline
TW200739419A (en) * 2006-04-07 2007-10-16 Univ Feng Chia Prediction mechanism of a program backward jump instruction
US7533252B2 (en) * 2006-08-31 2009-05-12 Intel Corporation Overriding a static prediction with a level-two predictor
US7617387B2 (en) * 2006-09-27 2009-11-10 Qualcomm Incorporated Methods and system for resolving simultaneous predicted branch instructions
US7707396B2 (en) * 2006-11-17 2010-04-27 International Business Machines Corporation Data processing system, processor and method of data processing having improved branch target address cache
CN101589367A (zh) * 2007-09-11 2009-11-25 夏寿民 复合断言和动态系统的系统定义和gui
US8136103B2 (en) * 2008-03-28 2012-03-13 International Business Machines Corporation Combining static and dynamic compilation to remove delinquent loads
US8127106B2 (en) 2008-04-18 2012-02-28 International Business Machines Corporation Access speculation predictor with predictions based on a domain indicator of a cache line
US8122223B2 (en) 2008-04-18 2012-02-21 International Business Machines Corporation Access speculation predictor with predictions based on memory region prior requestor tag information
US8131974B2 (en) 2008-04-18 2012-03-06 International Business Machines Corporation Access speculation predictor implemented via idle command processing resources
US8122222B2 (en) 2008-04-18 2012-02-21 International Business Machines Corporation Access speculation predictor with predictions based on a scope predictor
US9317288B2 (en) 2011-04-07 2016-04-19 Via Technologies, Inc. Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9176733B2 (en) 2011-04-07 2015-11-03 Via Technologies, Inc. Load multiple and store multiple instructions in a microprocessor that emulates banked registers
US8880851B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9146742B2 (en) 2011-04-07 2015-09-29 Via Technologies, Inc. Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA
US9128701B2 (en) 2011-04-07 2015-09-08 Via Technologies, Inc. Generating constant for microinstructions from modified immediate field during instruction translation
US9244686B2 (en) 2011-04-07 2016-01-26 Via Technologies, Inc. Microprocessor that translates conditional load/store instructions into variable number of microinstructions
US9274795B2 (en) * 2011-04-07 2016-03-01 Via Technologies, Inc. Conditional non-branch instruction prediction
US9378019B2 (en) 2011-04-07 2016-06-28 Via Technologies, Inc. Conditional load instructions in an out-of-order execution microprocessor
US9032189B2 (en) 2011-04-07 2015-05-12 Via Technologies, Inc. Efficient conditional ALU instruction in read-port limited register file microprocessor
US9141389B2 (en) 2011-04-07 2015-09-22 Via Technologies, Inc. Heterogeneous ISA microprocessor with shared hardware ISA registers
US9336180B2 (en) 2011-04-07 2016-05-10 Via Technologies, Inc. Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode
US9645822B2 (en) 2011-04-07 2017-05-09 Via Technologies, Inc Conditional store instructions in an out-of-order execution microprocessor
US9043580B2 (en) 2011-04-07 2015-05-26 Via Technologies, Inc. Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
US9898291B2 (en) 2011-04-07 2018-02-20 Via Technologies, Inc. Microprocessor with arm and X86 instruction length decoders
US9292470B2 (en) 2011-04-07 2016-03-22 Via Technologies, Inc. Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program
JP2013058135A (ja) * 2011-09-09 2013-03-28 Ritsumeikan 分岐予測器及びプロセッサ
US9032191B2 (en) * 2012-01-23 2015-05-12 International Business Machines Corporation Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels
US9384002B2 (en) 2012-11-16 2016-07-05 International Business Machines Corporation Speculative finish of instruction execution in a processor core
US9542290B1 (en) 2016-01-29 2017-01-10 International Business Machines Corporation Replicating test case data into a cache with non-naturally aligned data boundaries
US10169180B2 (en) 2016-05-11 2019-01-01 International Business Machines Corporation Replicating test code and test data into a cache with non-naturally aligned data boundaries
US10055320B2 (en) 2016-07-12 2018-08-21 International Business Machines Corporation Replicating test case data into a cache and cache inhibited memory
US10223225B2 (en) 2016-11-07 2019-03-05 International Business Machines Corporation Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundaries
US10261878B2 (en) 2017-03-14 2019-04-16 International Business Machines Corporation Stress testing a processor memory with a link stack
US11086629B2 (en) * 2018-11-09 2021-08-10 Arm Limited Misprediction of predicted taken branches in a data processing apparatus
US11163577B2 (en) 2018-11-26 2021-11-02 International Business Machines Corporation Selectively supporting static branch prediction settings only in association with processor-designated types of instructions
CN113868899B (zh) * 2021-12-03 2022-03-04 苏州浪潮智能科技有限公司 一种分支指令处理方法、系统、设备及计算机存储介质

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5507028A (en) * 1992-03-30 1996-04-09 International Business Machines Corporation History based branch prediction accessed via a history based earlier instruction address
KR100310581B1 (ko) * 1993-05-14 2001-12-17 피터 엔. 데트킨 분기목표버퍼의추측기록메카니즘
US5454117A (en) * 1993-08-25 1995-09-26 Nexgen, Inc. Configurable branch prediction for a processor performing speculative execution
TW261676B (de) * 1993-11-02 1995-11-01 Motorola Inc
IE940855A1 (en) * 1993-12-20 1995-06-28 Motorola Inc Data processor with speculative instruction fetching and¹method of operation
JPH08241198A (ja) * 1995-03-06 1996-09-17 Fujitsu Ltd 分岐命令処理方法
US5634103A (en) * 1995-11-09 1997-05-27 International Business Machines Corporation Method and system for minimizing branch misprediction penalties within a processor

Also Published As

Publication number Publication date
DE69719235T2 (de) 2003-10-30
JPH10133873A (ja) 1998-05-22
DE69719235D1 (de) 2003-04-03
KR970071251A (ko) 1997-11-07
TW344060B (en) 1998-11-01
JP3397081B2 (ja) 2003-04-14
KR100270003B1 (ko) 2000-10-16
US5752014A (en) 1998-05-12
EP0805390B1 (de) 2003-02-26
EP0805390A1 (de) 1997-11-05

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