DE69613071T2 - Prozessor und Kontrollverfahren zur Ausführung richtiger Saturationsoperation - Google Patents

Prozessor und Kontrollverfahren zur Ausführung richtiger Saturationsoperation

Info

Publication number
DE69613071T2
DE69613071T2 DE69613071T DE69613071T DE69613071T2 DE 69613071 T2 DE69613071 T2 DE 69613071T2 DE 69613071 T DE69613071 T DE 69613071T DE 69613071 T DE69613071 T DE 69613071T DE 69613071 T2 DE69613071 T2 DE 69613071T2
Authority
DE
Germany
Prior art keywords
processor
control method
saturation operation
performing correct
correct saturation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69613071T
Other languages
English (en)
Other versions
DE69613071D1 (de
Inventor
Satoshi Ogura
Shinya Miyaji
Nobuo Higaki
Masato Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69613071D1 publication Critical patent/DE69613071D1/de
Application granted granted Critical
Publication of DE69613071T2 publication Critical patent/DE69613071T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow
    • G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Executing Machine-Instructions (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
DE69613071T 1995-09-29 1996-09-27 Prozessor und Kontrollverfahren zur Ausführung richtiger Saturationsoperation Expired - Lifetime DE69613071T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7252737A JPH0997178A (ja) 1995-09-29 1995-09-29 飽和演算処理装置および方法

Publications (2)

Publication Number Publication Date
DE69613071D1 DE69613071D1 (de) 2001-07-05
DE69613071T2 true DE69613071T2 (de) 2001-09-20

Family

ID=17241572

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69613071T Expired - Lifetime DE69613071T2 (de) 1995-09-29 1996-09-27 Prozessor und Kontrollverfahren zur Ausführung richtiger Saturationsoperation

Country Status (7)

Country Link
US (1) US5847978A (de)
EP (1) EP0766169B1 (de)
JP (1) JPH0997178A (de)
KR (1) KR970016944A (de)
CN (2) CN1114152C (de)
DE (1) DE69613071T2 (de)
TW (1) TW317625B (de)

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CN1210647C (zh) 1996-11-29 2005-07-13 松下电器产业株式会社 适于作由正值处理及饱和运算处理组成的修整处理的处理器
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US6301597B1 (en) * 1997-11-18 2001-10-09 Intrinsity, Inc. Method and apparatus for saturation in an N-NARY adder/subtractor
US6301600B1 (en) * 1997-11-18 2001-10-09 Intrinsity, Inc. Method and apparatus for dynamic partitionable saturating adder/subtractor
US6115731A (en) * 1998-04-07 2000-09-05 Lucent Technologies Inc. Scalable overflow clamp and method for a digital gain scaler/summer
US6535900B1 (en) * 1998-09-07 2003-03-18 Dsp Group Ltd. Accumulation saturation by means of feedback
US6529930B1 (en) * 1998-11-16 2003-03-04 Hitachi America, Ltd. Methods and apparatus for performing a signed saturation operation
US6314443B1 (en) 1998-11-20 2001-11-06 Arm Limited Double/saturate/add/saturate and double/saturate/subtract/saturate operations in a data processing system
US6519620B1 (en) * 1999-04-22 2003-02-11 International Business Machines Corporation Saturation select apparatus and method therefor
US6499046B1 (en) 1999-05-20 2002-12-24 International Business Machines Corporation Saturation detection apparatus and method therefor
DE10041511C1 (de) 2000-08-24 2001-08-09 Infineon Technologies Ag Additionsschaltung für digitale Daten
US7206800B1 (en) * 2000-08-30 2007-04-17 Micron Technology, Inc. Overflow detection and clamping with parallel operand processing for fixed-point multipliers
US7039906B1 (en) 2000-09-29 2006-05-02 International Business Machines Corporation Compiler for enabling multiple signed independent data elements per register
US6834337B1 (en) 2000-09-29 2004-12-21 International Business Machines Corporation System and method for enabling multiple signed independent data elements per register
JP3779602B2 (ja) * 2001-11-28 2006-05-31 松下電器産業株式会社 Ｓｉｍｄ演算方法およびｓｉｍｄ演算装置
FR2835938A1 (fr) * 2002-02-08 2003-08-15 St Microelectronics Sa Operateur saturant a haute efficacite
EP1387259B1 (de) * 2002-07-31 2017-09-20 Texas Instruments Incorporated Zwischen-Prozessor Steuerung
US6986023B2 (en) * 2002-08-09 2006-01-10 Intel Corporation Conditional execution of coprocessor instruction based on main processor arithmetic flags
US7461118B2 (en) * 2003-04-09 2008-12-02 Infineon Technologies Ag Arithmetic logic unit with merged circuitry for comparison, minimum/maximum selection and saturation for signed and unsigned numbers
US7467176B2 (en) * 2004-02-20 2008-12-16 Altera Corporation Saturation and rounding in multiply-accumulate blocks
US20050210089A1 (en) * 2004-03-19 2005-09-22 Arm Limited Saturating shift mechanisms within data processing systems
US7689640B2 (en) * 2005-06-06 2010-03-30 Atmel Corporation Method and apparatus for formatting numbers in microprocessors
US8620980B1 (en) 2005-09-27 2013-12-31 Altera Corporation Programmable device with specialized multiplier blocks
US8266198B2 (en) 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8301681B1 (en) 2006-02-09 2012-10-30 Altera Corporation Specialized processing block for programmable logic device
US8041759B1 (en) 2006-02-09 2011-10-18 Altera Corporation Specialized processing block for programmable logic device
US8266199B2 (en) 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8386550B1 (en) 2006-09-20 2013-02-26 Altera Corporation Method for configuring a finite impulse response filter in a programmable logic device
US7930336B2 (en) 2006-12-05 2011-04-19 Altera Corporation Large multiplier for programmable logic device
US8386553B1 (en) 2006-12-05 2013-02-26 Altera Corporation Large multiplier for programmable logic device
US8650231B1 (en) 2007-01-22 2014-02-11 Altera Corporation Configuring floating point operations in a programmable device
US8645450B1 (en) 2007-03-02 2014-02-04 Altera Corporation Multiplier-accumulator circuitry and methods
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8307023B1 (en) 2008-10-10 2012-11-06 Altera Corporation DSP block for implementing large multiplier on a programmable integrated circuit device
JP5556025B2 (ja) * 2009-02-27 2014-07-23 日本電気株式会社 ストレージシステム
US8468192B1 (en) 2009-03-03 2013-06-18 Altera Corporation Implementing multipliers in a programmable integrated circuit device
US8645449B1 (en) 2009-03-03 2014-02-04 Altera Corporation Combined floating point adder and subtractor
US8706790B1 (en) 2009-03-03 2014-04-22 Altera Corporation Implementing mixed-precision floating-point operations in a programmable integrated circuit device
US8650236B1 (en) 2009-08-04 2014-02-11 Altera Corporation High-rate interpolation or decimation filter in integrated circuit device
US8396914B1 (en) 2009-09-11 2013-03-12 Altera Corporation Matrix decomposition in an integrated circuit device
US8412756B1 (en) 2009-09-11 2013-04-02 Altera Corporation Multi-operand floating point operations in a programmable integrated circuit device
US8539016B1 (en) 2010-02-09 2013-09-17 Altera Corporation QR decomposition in an integrated circuit device
US8601044B2 (en) 2010-03-02 2013-12-03 Altera Corporation Discrete Fourier Transform in an integrated circuit device
US8484265B1 (en) 2010-03-04 2013-07-09 Altera Corporation Angular range reduction in an integrated circuit device
US8510354B1 (en) 2010-03-12 2013-08-13 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8539014B2 (en) 2010-03-25 2013-09-17 Altera Corporation Solving linear matrices in an integrated circuit device
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8589463B2 (en) 2010-06-25 2013-11-19 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8577951B1 (en) 2010-08-19 2013-11-05 Altera Corporation Matrix operations in an integrated circuit device
US8645451B2 (en) 2011-03-10 2014-02-04 Altera Corporation Double-clocked specialized processing block in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US8812576B1 (en) 2011-09-12 2014-08-19 Altera Corporation QR decomposition in an integrated circuit device
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8762443B1 (en) 2011-11-15 2014-06-24 Altera Corporation Matrix operations in an integrated circuit device
US8543634B1 (en) 2012-03-30 2013-09-24 Altera Corporation Specialized processing block for programmable integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9747074B2 (en) 2014-02-25 2017-08-29 Kabushiki Kaisha Toshiba Division circuit and microprocessor
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
CN106406813B (zh) * 2016-08-31 2019-01-29 宁波菲仕电机技术有限公司 一种通用伺服控制算术逻辑单元
US10942706B2 (en) 2017-05-05 2021-03-09 Intel Corporation Implementation of floating-point trigonometric functions in an integrated circuit device
CN112181354B (zh) * 2020-10-12 2021-08-10 上海芯旺微电子技术有限公司 一种移位饱和同步处理的方法及其应用

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Also Published As

Publication number Publication date
US5847978A (en) 1998-12-08
JPH0997178A (ja) 1997-04-08
EP0766169B1 (de) 2001-05-30
CN1515999A (zh) 2004-07-28
DE69613071D1 (de) 2001-07-05
CN1159031A (zh) 1997-09-10
EP0766169A1 (de) 1997-04-02
KR970016944A (ko) 1997-04-28
CN1114152C (zh) 2003-07-09
TW317625B (de) 1997-10-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP