ATE156609T1 - Verfahren und anordnung zur kontrolle der umwandlung virtueller adressen in physikalische adressen in einem computersystem - Google Patents

Verfahren und anordnung zur kontrolle der umwandlung virtueller adressen in physikalische adressen in einem computersystem

Info

Publication number
ATE156609T1
ATE156609T1 AT90300954T AT90300954T ATE156609T1 AT E156609 T1 ATE156609 T1 AT E156609T1 AT 90300954 T AT90300954 T AT 90300954T AT 90300954 T AT90300954 T AT 90300954T AT E156609 T1 ATE156609 T1 AT E156609T1
Authority
AT
Austria
Prior art keywords
translation buffer
memory
virtual
physical
addresses
Prior art date
Application number
AT90300954T
Other languages
German (de)
English (en)
Inventor
Ricky C Hetherington
David A Webb Jr
David B Fite
John E Murray
Tryggve Fossum
Dwight P Manley
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE156609T1 publication Critical patent/ATE156609T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Image Input (AREA)
AT90300954T 1989-02-03 1990-01-30 Verfahren und anordnung zur kontrolle der umwandlung virtueller adressen in physikalische adressen in einem computersystem ATE156609T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30654489A 1989-02-03 1989-02-03
AU53950/90A AU632558B2 (en) 1989-02-03 1990-04-27 Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system

Publications (1)

Publication Number Publication Date
ATE156609T1 true ATE156609T1 (de) 1997-08-15

Family

ID=25630274

Family Applications (1)

Application Number Title Priority Date Filing Date
AT90300954T ATE156609T1 (de) 1989-02-03 1990-01-30 Verfahren und anordnung zur kontrolle der umwandlung virtueller adressen in physikalische adressen in einem computersystem

Country Status (7)

Country Link
US (1) US5349651A (cg-RX-API-DMAC7.html)
EP (1) EP0381447B1 (cg-RX-API-DMAC7.html)
JP (1) JPH02232753A (cg-RX-API-DMAC7.html)
AT (1) ATE156609T1 (cg-RX-API-DMAC7.html)
AU (1) AU632558B2 (cg-RX-API-DMAC7.html)
CA (1) CA1325288C (cg-RX-API-DMAC7.html)
DE (1) DE69031183T2 (cg-RX-API-DMAC7.html)

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US6157986A (en) * 1997-12-16 2000-12-05 Advanced Micro Devices, Inc. Fast linear tag validation unit for use in microprocessor
US6263408B1 (en) * 1999-03-31 2001-07-17 International Business Machines Corporation Method and apparatus for implementing automatic cache variable update
US6233668B1 (en) 1999-10-27 2001-05-15 Compaq Computer Corporation Concurrent page tables
US6628294B1 (en) 1999-12-31 2003-09-30 Intel Corporation Prefetching of virtual-to-physical address translation for display data
US6615300B1 (en) * 2000-06-19 2003-09-02 Transmeta Corporation Fast look-up of indirect branch destination in a dynamic translation system
US9131899B2 (en) 2011-07-06 2015-09-15 Apple Inc. Efficient handling of misaligned loads and stores
US7404064B2 (en) * 2004-04-07 2008-07-22 Stmicroelectronics S.A. Method and device for calculating addresses of a segmented program memory
US10621092B2 (en) 2008-11-24 2020-04-14 Intel Corporation Merging level cache and data cache units having indicator bits related to speculative execution
US9672019B2 (en) 2008-11-24 2017-06-06 Intel Corporation Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads
US8775153B2 (en) * 2009-12-23 2014-07-08 Intel Corporation Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment
US9921967B2 (en) 2011-07-26 2018-03-20 Intel Corporation Multi-core shared page miss handler
US9417855B2 (en) 2011-09-30 2016-08-16 Intel Corporation Instruction and logic to perform dynamic binary translation
US9292453B2 (en) 2013-02-01 2016-03-22 International Business Machines Corporation Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)
US9405551B2 (en) 2013-03-12 2016-08-02 Intel Corporation Creating an isolated execution environment in a co-designed processor
US9891936B2 (en) 2013-09-27 2018-02-13 Intel Corporation Method and apparatus for page-level monitoring
KR102614631B1 (ko) * 2013-10-21 2023-12-19 에프엘씨 글로벌 리미티드 최종 레벨 캐시 시스템 및 이에 대응하는 방법
CN116166179A (zh) * 2021-11-25 2023-05-26 华为技术有限公司 数据存储系统、智能网卡及计算节点
CN117971719B (zh) * 2024-03-28 2024-06-28 北京微核芯科技有限公司 一种提前传递数据的方法及其装置

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Also Published As

Publication number Publication date
AU632558B2 (en) 1993-01-07
CA1325288C (en) 1993-12-14
EP0381447B1 (en) 1997-08-06
EP0381447A3 (en) 1992-05-13
DE69031183D1 (de) 1997-09-11
JPH0564815B2 (cg-RX-API-DMAC7.html) 1993-09-16
JPH02232753A (ja) 1990-09-14
EP0381447A2 (en) 1990-08-08
DE69031183T2 (de) 1998-03-12
US5349651A (en) 1994-09-20
AU5395090A (en) 1991-12-19

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties