AU632558B2 - Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system - Google Patents

Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system Download PDF

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Publication number
AU632558B2
AU632558B2 AU53950/90A AU5395090A AU632558B2 AU 632558 B2 AU632558 B2 AU 632558B2 AU 53950/90 A AU53950/90 A AU 53950/90A AU 5395090 A AU5395090 A AU 5395090A AU 632558 B2 AU632558 B2 AU 632558B2
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AU
Australia
Prior art keywords
memory
address
virtual
virtual address
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU53950/90A
Other languages
English (en)
Other versions
AU5395090A (en
Inventor
David B. Fite
Tryggve Fossum
Ricky C. Hetherington
Dwight P. Manley
John E. Murray
David A. Webb Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to CA000608692A priority Critical patent/CA1325288C/en
Priority to JP1257635A priority patent/JPH02232753A/ja
Priority to DE69031183T priority patent/DE69031183T2/de
Priority to EP90300954A priority patent/EP0381447B1/en
Priority to AT90300954T priority patent/ATE156609T1/de
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Priority to AU53950/90A priority patent/AU632558B2/en
Priority to US07/746,007 priority patent/US5349651A/en
Publication of AU5395090A publication Critical patent/AU5395090A/en
Application granted granted Critical
Publication of AU632558B2 publication Critical patent/AU632558B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Image Input (AREA)
AU53950/90A 1989-02-03 1990-04-27 Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system Ceased AU632558B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CA000608692A CA1325288C (en) 1989-02-03 1989-08-18 Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system
JP1257635A JPH02232753A (ja) 1989-02-03 1989-10-02 デジタルコンピュータシステムにおける仮想メモリーアドレスから物理的メモリーアドレスへの変換を制御する方法とその装置
EP90300954A EP0381447B1 (en) 1989-02-03 1990-01-30 Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system
AT90300954T ATE156609T1 (de) 1989-02-03 1990-01-30 Verfahren und anordnung zur kontrolle der umwandlung virtueller adressen in physikalische adressen in einem computersystem
DE69031183T DE69031183T2 (de) 1989-02-03 1990-01-30 Verfahren und Anordnung zur Kontrolle der Umwandlung virtueller Adressen in physikalische Adressen in einem Computersystem
AU53950/90A AU632558B2 (en) 1989-02-03 1990-04-27 Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system
US07/746,007 US5349651A (en) 1989-02-03 1991-08-09 System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30654489A 1989-02-03 1989-02-03
AU53950/90A AU632558B2 (en) 1989-02-03 1990-04-27 Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system

Publications (2)

Publication Number Publication Date
AU5395090A AU5395090A (en) 1991-12-19
AU632558B2 true AU632558B2 (en) 1993-01-07

Family

ID=25630274

Family Applications (1)

Application Number Title Priority Date Filing Date
AU53950/90A Ceased AU632558B2 (en) 1989-02-03 1990-04-27 Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system

Country Status (7)

Country Link
US (1) US5349651A (cg-RX-API-DMAC7.html)
EP (1) EP0381447B1 (cg-RX-API-DMAC7.html)
JP (1) JPH02232753A (cg-RX-API-DMAC7.html)
AT (1) ATE156609T1 (cg-RX-API-DMAC7.html)
AU (1) AU632558B2 (cg-RX-API-DMAC7.html)
CA (1) CA1325288C (cg-RX-API-DMAC7.html)
DE (1) DE69031183T2 (cg-RX-API-DMAC7.html)

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US6175906B1 (en) * 1996-12-06 2001-01-16 Advanced Micro Devices, Inc. Mechanism for fast revalidation of virtual tags
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US6311258B1 (en) 1997-04-03 2001-10-30 Canon Kabushiki Kaisha Data buffer apparatus and method for storing graphical data using data encoders and decoders
US6246396B1 (en) 1997-04-30 2001-06-12 Canon Kabushiki Kaisha Cached color conversion method and apparatus
US6707463B1 (en) 1997-04-30 2004-03-16 Canon Kabushiki Kaisha Data normalization technique
US6674536B2 (en) 1997-04-30 2004-01-06 Canon Kabushiki Kaisha Multi-instruction stream processor
AUPO647997A0 (en) * 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Memory controller architecture
US6289138B1 (en) 1997-04-30 2001-09-11 Canon Kabushiki Kaisha General image processor
KR100231707B1 (ko) * 1997-08-04 2000-01-15 정선종 통신 장비의 디엠에이 처리 방법 및 그 장치
US6157986A (en) * 1997-12-16 2000-12-05 Advanced Micro Devices, Inc. Fast linear tag validation unit for use in microprocessor
US6263408B1 (en) * 1999-03-31 2001-07-17 International Business Machines Corporation Method and apparatus for implementing automatic cache variable update
US6233668B1 (en) 1999-10-27 2001-05-15 Compaq Computer Corporation Concurrent page tables
US6628294B1 (en) 1999-12-31 2003-09-30 Intel Corporation Prefetching of virtual-to-physical address translation for display data
US6615300B1 (en) * 2000-06-19 2003-09-02 Transmeta Corporation Fast look-up of indirect branch destination in a dynamic translation system
US9131899B2 (en) 2011-07-06 2015-09-15 Apple Inc. Efficient handling of misaligned loads and stores
US7404064B2 (en) * 2004-04-07 2008-07-22 Stmicroelectronics S.A. Method and device for calculating addresses of a segmented program memory
US10621092B2 (en) 2008-11-24 2020-04-14 Intel Corporation Merging level cache and data cache units having indicator bits related to speculative execution
US9672019B2 (en) 2008-11-24 2017-06-06 Intel Corporation Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads
US8775153B2 (en) * 2009-12-23 2014-07-08 Intel Corporation Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment
US9921967B2 (en) 2011-07-26 2018-03-20 Intel Corporation Multi-core shared page miss handler
US9417855B2 (en) 2011-09-30 2016-08-16 Intel Corporation Instruction and logic to perform dynamic binary translation
US9292453B2 (en) 2013-02-01 2016-03-22 International Business Machines Corporation Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)
US9405551B2 (en) 2013-03-12 2016-08-02 Intel Corporation Creating an isolated execution environment in a co-designed processor
US9891936B2 (en) 2013-09-27 2018-02-13 Intel Corporation Method and apparatus for page-level monitoring
KR102614631B1 (ko) * 2013-10-21 2023-12-19 에프엘씨 글로벌 리미티드 최종 레벨 캐시 시스템 및 이에 대응하는 방법
CN116166179A (zh) * 2021-11-25 2023-05-26 华为技术有限公司 数据存储系统、智能网卡及计算节点
CN117971719B (zh) * 2024-03-28 2024-06-28 北京微核芯科技有限公司 一种提前传递数据的方法及其装置

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Also Published As

Publication number Publication date
CA1325288C (en) 1993-12-14
EP0381447B1 (en) 1997-08-06
ATE156609T1 (de) 1997-08-15
EP0381447A3 (en) 1992-05-13
DE69031183D1 (de) 1997-09-11
JPH0564815B2 (cg-RX-API-DMAC7.html) 1993-09-16
JPH02232753A (ja) 1990-09-14
EP0381447A2 (en) 1990-08-08
DE69031183T2 (de) 1998-03-12
US5349651A (en) 1994-09-20
AU5395090A (en) 1991-12-19

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