ATE142801T1 - Verfahren zur identifizierung schlechter daten - Google Patents

Verfahren zur identifizierung schlechter daten

Info

Publication number
ATE142801T1
ATE142801T1 AT89306719T AT89306719T ATE142801T1 AT E142801 T1 ATE142801 T1 AT E142801T1 AT 89306719 T AT89306719 T AT 89306719T AT 89306719 T AT89306719 T AT 89306719T AT E142801 T1 ATE142801 T1 AT E142801T1
Authority
AT
Austria
Prior art keywords
bad data
identifying bad
rewritten
identifying
methodology
Prior art date
Application number
AT89306719T
Other languages
English (en)
Inventor
Michael A Gagliardo
Paul M Goodwin
Donald W Smelser
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE142801T1 publication Critical patent/ATE142801T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/1056—Updating check bits on partial write, i.e. read/modify/write
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1024—Identification of the type of error

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
AT89306719T 1989-01-27 1989-07-03 Verfahren zur identifizierung schlechter daten ATE142801T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/303,574 US5014273A (en) 1989-01-27 1989-01-27 Bad data algorithm

Publications (1)

Publication Number Publication Date
ATE142801T1 true ATE142801T1 (de) 1996-09-15

Family

ID=23172719

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89306719T ATE142801T1 (de) 1989-01-27 1989-07-03 Verfahren zur identifizierung schlechter daten

Country Status (6)

Country Link
US (1) US5014273A (de)
EP (1) EP0381885B1 (de)
JP (1) JP2772391B2 (de)
AT (1) ATE142801T1 (de)
CA (1) CA1319436C (de)
DE (1) DE68927164T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
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US5325375A (en) * 1991-06-28 1994-06-28 Sun Microsystems, Inc. Method and apparatus for non-atomic level parity protection for storing data in a random access memory
JPH05216698A (ja) * 1991-08-05 1993-08-27 Advanced Micro Devicds Inc 改良されたエラー検出および訂正回路
ES2150430T3 (es) * 1992-06-30 2000-12-01 Siemens Ag Procedimiento para el aseguramiento de los datos en memorias de escritura y de lectura.
US5644583A (en) * 1992-09-22 1997-07-01 International Business Machines Corporation Soft error correction technique and system for odd weight row error correction codes
US6151689A (en) * 1992-12-17 2000-11-21 Tandem Computers Incorporated Detecting and isolating errors occurring in data communication in a multiple processor system
US5379304A (en) * 1994-01-28 1995-01-03 International Business Machines Corporation Method and structure for providing error correction code and parity for each byte on SIMM's
US5623506A (en) * 1994-01-28 1997-04-22 International Business Machines Corporation Method and structure for providing error correction code within a system having SIMMs
US5550716A (en) * 1994-11-18 1996-08-27 Ford Motor Company Reduced package depth low profile headlamp
US5875477A (en) * 1995-12-22 1999-02-23 Intel Corporation Method and apparatus for error management in a solid state disk drive using primary and secondary logical sector numbers
US6678854B1 (en) * 1999-10-12 2004-01-13 Ericsson, Inc. Methods and systems for providing a second data signal on a frame of bits including a first data signal and an error-correcting code
US7168026B2 (en) * 2001-06-22 2007-01-23 Intel Corporation Method and apparatus for preservation of failure state in a read destructive memory
DE10252230A1 (de) * 2002-11-11 2004-05-27 Robert Bosch Gmbh Verfahren zur Übertragung von Daten
US7587658B1 (en) * 2005-01-03 2009-09-08 Sun Microsystems, Inc. ECC encoding for uncorrectable errors
US20080168331A1 (en) * 2007-01-05 2008-07-10 Thomas Vogelsang Memory including error correction code circuit
US8312349B2 (en) 2009-10-27 2012-11-13 Micron Technology, Inc. Error detection/correction based memory management
US8751736B2 (en) 2011-08-02 2014-06-10 Oracle International Corporation Instructions to set and read memory version information
US8572441B2 (en) 2011-08-05 2013-10-29 Oracle International Corporation Maximizing encodings of version control bits for memory corruption detection
US9391638B1 (en) * 2011-11-10 2016-07-12 Marvell Israel (M.I.S.L) Ltd. Error indications in error correction code (ECC) protected memory systems
US9043559B2 (en) 2012-10-23 2015-05-26 Oracle International Corporation Block memory engine with memory corruption detection
US9672298B2 (en) 2014-05-01 2017-06-06 Oracle International Corporation Precise excecution of versioned store instructions
US9195593B1 (en) 2014-09-27 2015-11-24 Oracle International Corporation Hardware assisted object memory migration
US10127101B2 (en) * 2015-08-28 2018-11-13 Intel Corporation Memory device error check and scrub mode and error transparency
US10297335B2 (en) 2016-09-02 2019-05-21 International Business Machines Corporation Tracking address ranges for computer memory errors
US10353669B2 (en) 2016-09-02 2019-07-16 International Business Machines Corporation Managing entries in a mark table of computer memory errors
US10338999B2 (en) 2016-09-02 2019-07-02 International Business Machines Corporation Confirming memory marks indicating an error in computer memory
US10304560B2 (en) 2016-09-02 2019-05-28 International Business Machines Corporation Performing error correction in computer memory
KR20230046362A (ko) * 2021-09-29 2023-04-06 삼성전자주식회사 메모리 모듈의 동작 방법, 메모리 컨트롤러의 동작 방법, 및 메모리 시스템의 동작 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3906200A (en) * 1974-07-05 1975-09-16 Sperry Rand Corp Error logging in semiconductor storage units
JPS51137335A (en) * 1975-05-22 1976-11-27 Yoshihiro Toma Faulty memory permissible control system
US4077028A (en) * 1976-06-14 1978-02-28 Ncr Corporation Error checking and correcting device
US4319357A (en) * 1979-12-14 1982-03-09 International Business Machines Corp. Double error correction using single error correcting code
US4458349A (en) * 1982-06-16 1984-07-03 International Business Machines Corporation Method for storing data words in fault tolerant memory to recover uncorrectable errors
JPS6050669A (ja) * 1983-08-29 1985-03-20 Hitachi Ltd デ−タ復調方式
US4604751A (en) * 1984-06-29 1986-08-05 International Business Machines Corporation Error logging memory system for avoiding miscorrection of triple errors
DE3482509D1 (de) * 1984-12-28 1990-07-19 Ibm Geraet zum korrigieren von fehlern in speichern.
US4661955A (en) * 1985-01-18 1987-04-28 Ibm Corporation Extended error correction for package error correction codes
US4713816A (en) * 1986-02-25 1987-12-15 U.S. Philips Corporation Three module memory system constructed with symbol-wide memory chips and having an error protection feature, each symbol consisting of 2I+1 bits
US4780809A (en) * 1986-08-08 1988-10-25 Amdahl Corporation Apparatus for storing data with deferred uncorrectable error reporting
US4817095A (en) * 1987-05-15 1989-03-28 Digital Equipment Corporation Byte write error code method and apparatus
US4782487A (en) * 1987-05-15 1988-11-01 Digital Equipment Corporation Memory test method and apparatus

Also Published As

Publication number Publication date
DE68927164D1 (de) 1996-10-17
JPH02206843A (ja) 1990-08-16
CA1319436C (en) 1993-06-22
EP0381885A3 (de) 1991-09-18
DE68927164T2 (de) 1997-04-10
US5014273A (en) 1991-05-07
EP0381885A2 (de) 1990-08-16
EP0381885B1 (de) 1996-09-11
JP2772391B2 (ja) 1998-07-02

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties