AT249411B - Prüfschaltung für ein dezimales Addierwerk - Google Patents

Prüfschaltung für ein dezimales Addierwerk

Info

Publication number
AT249411B
AT249411B AT994364A AT994364A AT249411B AT 249411 B AT249411 B AT 249411B AT 994364 A AT994364 A AT 994364A AT 994364 A AT994364 A AT 994364A AT 249411 B AT249411 B AT 249411B
Authority
AT
Austria
Prior art keywords
test circuit
decimal adder
decimal
adder
test
Prior art date
Application number
AT994364A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of AT249411B publication Critical patent/AT249411B/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4921—Single digit adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Quality & Reliability (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)
  • Reciprocating, Oscillating Or Vibrating Motors (AREA)
AT994364A 1963-12-04 1964-11-24 Prüfschaltung für ein dezimales Addierwerk AT249411B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US327915A US3300625A (en) 1963-12-04 1963-12-04 Apparatus for testing binary-coded decimal arithmetic digits by binary parity checking circuits

Publications (1)

Publication Number Publication Date
AT249411B true AT249411B (de) 1966-09-26

Family

ID=23278631

Family Applications (1)

Application Number Title Priority Date Filing Date
AT994364A AT249411B (de) 1963-12-04 1964-11-24 Prüfschaltung für ein dezimales Addierwerk

Country Status (9)

Country Link
US (1) US3300625A (de)
AT (1) AT249411B (de)
BE (1) BE656664A (de)
CH (1) CH421568A (de)
DE (1) DE1270306B (de)
ES (1) ES306696A1 (de)
GB (1) GB1054203A (de)
NL (1) NL155959B (de)
SE (1) SE319033B (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1524158B1 (de) * 1966-06-03 1970-08-06 Ibm Addier-Subtrahier-Schaltung für kodierte Dezimalzahlen insbesondere solche in Byte-Darstellung
FR2056229A5 (de) * 1969-07-31 1971-05-14 Ibm
US3986015A (en) * 1975-06-23 1976-10-12 International Business Machines Corporation Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection
US4799222A (en) * 1987-01-07 1989-01-17 Honeywell Bull Inc. Address transform method and apparatus for transferring addresses

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL197751A (de) * 1954-06-04
IT557030A (de) * 1955-08-01
US2914248A (en) * 1956-03-07 1959-11-24 Ibm Program control for a data processing machine
GB802705A (en) * 1956-05-14 1958-10-08 British Tabulating Mach Co Ltd Improvements in or relating to digital calculating apparatus
US3046523A (en) * 1958-06-23 1962-07-24 Ibm Counter checking circuit
US3061193A (en) * 1958-10-21 1962-10-30 Bell Telephone Labor Inc Magnetic core arithmetic unit
US3063636A (en) * 1959-07-06 1962-11-13 Ibm Matrix arithmetic system with input and output error checking circuits
US3078039A (en) * 1960-06-27 1963-02-19 Ibm Error checking system for a parallel adder

Also Published As

Publication number Publication date
SE319033B (de) 1969-12-22
ES306696A1 (es) 1965-04-16
CH421568A (de) 1966-09-30
US3300625A (en) 1967-01-24
NL6414095A (de) 1965-06-07
BE656664A (de) 1965-04-01
DE1270306B (de) 1968-06-12
NL155959B (nl) 1978-02-15
GB1054203A (de)

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