CH432066A - Prüfeinrichtung für Addierwerk - Google Patents

Prüfeinrichtung für Addierwerk

Info

Publication number
CH432066A
CH432066A CH799864A CH799864A CH432066A CH 432066 A CH432066 A CH 432066A CH 799864 A CH799864 A CH 799864A CH 799864 A CH799864 A CH 799864A CH 432066 A CH432066 A CH 432066A
Authority
CH
Switzerland
Prior art keywords
adder
test device
test
Prior art date
Application number
CH799864A
Other languages
English (en)
Inventor
Herbert Pitkowsky Stanley
Brewster Godfrey Richard
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH432066A publication Critical patent/CH432066A/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)
CH799864A 1963-06-25 1964-06-18 Prüfeinrichtung für Addierwerk CH432066A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US290486A US3342983A (en) 1963-06-25 1963-06-25 Parity checking and parity generating means for binary adders

Publications (1)

Publication Number Publication Date
CH432066A true CH432066A (de) 1967-03-15

Family

ID=23116221

Family Applications (1)

Application Number Title Priority Date Filing Date
CH799864A CH432066A (de) 1963-06-25 1964-06-18 Prüfeinrichtung für Addierwerk

Country Status (6)

Country Link
US (1) US3342983A (de)
BE (1) BE649675A (de)
CH (1) CH432066A (de)
DE (1) DE1474037C3 (de)
NL (1) NL142799B (de)
SE (1) SE319031B (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1081665A (en) * 1965-04-05 1967-08-31 Ibm Data processing device
US3531631A (en) * 1967-01-11 1970-09-29 Ibm Parity checking system
US3476923A (en) * 1967-01-13 1969-11-04 Ibm High speed multi-input adder
US3555255A (en) * 1968-08-09 1971-01-12 Bell Telephone Labor Inc Error detection arrangement for data processing register
FR2056229A5 (de) * 1969-07-31 1971-05-14 Ibm
US3659089A (en) * 1970-12-23 1972-04-25 Ibm Error detecting and correcting system and method
US3699323A (en) * 1970-12-23 1972-10-17 Ibm Error detecting and correcting system and method
US3925647A (en) * 1974-09-30 1975-12-09 Honeywell Inf Systems Parity predicting and checking logic for carry look-ahead binary adder
US3986015A (en) * 1975-06-23 1976-10-12 International Business Machines Corporation Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection
JPS5283046A (en) * 1975-12-30 1977-07-11 Fujitsu Ltd Check system of error detection circuit
US4304002A (en) * 1978-11-23 1981-12-01 International Computers Limited Data processing system with error checking
US4234955A (en) * 1979-01-26 1980-11-18 International Business Machines Corporation Parity for computer system having an array of external registers
US4879675A (en) * 1988-02-17 1989-11-07 International Business Machines Corporation Parity generator circuit and method
DE10084213B4 (de) * 1999-12-29 2006-03-23 Systemonic Ag Anordnung und Verfahren zur Steuerung des Datenflusses

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3078039A (en) * 1960-06-27 1963-02-19 Ibm Error checking system for a parallel adder
US3196260A (en) * 1961-05-03 1965-07-20 Ibm Adder
US3145293A (en) * 1961-06-05 1964-08-18 Ibm Bi-directional binary counter
US3222652A (en) * 1961-08-07 1965-12-07 Ibm Special-function data processing
US3196259A (en) * 1962-05-09 1965-07-20 Sperry Rand Corp Parity checking system

Also Published As

Publication number Publication date
DE1474037C3 (de) 1974-04-11
BE649675A (de) 1964-10-16
DE1474037A1 (de) 1969-01-23
US3342983A (en) 1967-09-19
DE1474037B2 (de) 1973-08-30
NL6406850A (de) 1964-12-28
NL142799B (nl) 1974-07-15
SE319031B (de) 1969-12-22

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