AR025211A1 - UN PROCEDIMIENTO Y UN DISPOSITIVO PARA CODIFICAR DATOS DIGITALES FUENTE QUE UTILIZAN EN PARALELO, AL MENOS DOS ETAPAS DE CODIFICACIoN ELEMENTAL Y QUE COMPRENDE UNA ETAPA DE PERMUTA, UN PROCEDIMIENTO Y UN DISPOSITIVO DE DESCODIFICACIoN DE DATOS DIGITALES ORGANIZADOS EN PALABRAS DE CODIGO, UN DISPOSIT - Google Patents
UN PROCEDIMIENTO Y UN DISPOSITIVO PARA CODIFICAR DATOS DIGITALES FUENTE QUE UTILIZAN EN PARALELO, AL MENOS DOS ETAPAS DE CODIFICACIoN ELEMENTAL Y QUE COMPRENDE UNA ETAPA DE PERMUTA, UN PROCEDIMIENTO Y UN DISPOSITIVO DE DESCODIFICACIoN DE DATOS DIGITALES ORGANIZADOS EN PALABRAS DE CODIGO, UN DISPOSITInfo
- Publication number
- AR025211A1 AR025211A1 ARP000103733A ARP000103733A AR025211A1 AR 025211 A1 AR025211 A1 AR 025211A1 AR P000103733 A ARP000103733 A AR P000103733A AR P000103733 A ARP000103733 A AR P000103733A AR 025211 A1 AR025211 A1 AR 025211A1
- Authority
- AR
- Argentina
- Prior art keywords
- source
- procedure
- stage
- stages
- digital data
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
Un procedimiento y un dispositivo para codificar datos digitales fuente (15) que utilizan en paralelo al menos dos etapas (11, 12) de codificacionelemental donde cada una de ellas toma en cuenta todos los datos fuente (15) y que comprende una etapad e permuta (13) que modifica el orden en el que se tomanen cuenta dichos datos fuente entre las mencionadas etapas (11, 12) de codificacion elemental, en donde dichos datos fuente (15) se organizan en palabras decodigo fuente que comprenden cadauna n elementos binarios fuente, siendo n igual o superior a 2, y que dicha etapa de permuta (13) comprende: una etapa (132)de modificacion reversible del contenido de por lo menos algunas de dichas palabras de codigo fuente, que suministra palabrasde co digo modificadas; una etapa(131) de permuta del orden de dichas palabras de codigo fuente o modificadas. También se divulga un procedimiento y un dispositivo de descodificacion de datosdigitales fuente codificados y un dispositivo de emisiony/o rece pcion de datos digitales fuente codificados.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9909631A FR2796780B1 (fr) | 1999-07-21 | 1999-07-21 | Procede et dispositif de codage a au moins deux codages en parallele et permutation amelioree, et procede et dispositif de decodage correspondants |
Publications (1)
Publication Number | Publication Date |
---|---|
AR025211A1 true AR025211A1 (es) | 2002-11-13 |
Family
ID=9548486
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ARP000103733A AR025211A1 (es) | 1999-07-21 | 2000-07-20 | UN PROCEDIMIENTO Y UN DISPOSITIVO PARA CODIFICAR DATOS DIGITALES FUENTE QUE UTILIZAN EN PARALELO, AL MENOS DOS ETAPAS DE CODIFICACIoN ELEMENTAL Y QUE COMPRENDE UNA ETAPA DE PERMUTA, UN PROCEDIMIENTO Y UN DISPOSITIVO DE DESCODIFICACIoN DE DATOS DIGITALES ORGANIZADOS EN PALABRAS DE CODIGO, UN DISPOSIT |
Country Status (10)
Country | Link |
---|---|
US (1) | US6782504B1 (es) |
EP (1) | EP1205032B1 (es) |
JP (2) | JP2004511114A (es) |
CN (1) | CN1375130B (es) |
AR (1) | AR025211A1 (es) |
AU (1) | AU6578300A (es) |
DE (1) | DE60014395T2 (es) |
ES (1) | ES2226898T3 (es) |
FR (1) | FR2796780B1 (es) |
WO (1) | WO2001006661A1 (es) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8077743B2 (en) * | 2003-11-18 | 2011-12-13 | Qualcomm Incorporated | Method and apparatus for offset interleaving of vocoder frames |
US7836384B2 (en) * | 2004-05-28 | 2010-11-16 | France Telecom | Error-correction coding method comprising local error detection codes interconnected by state words, corresponding decoding method, transmitting, receiving and storage devices and program |
US7590044B2 (en) * | 2005-11-14 | 2009-09-15 | Motorola, Inc. | Method and apparatus for interleaving\within a communication system |
US7873897B2 (en) * | 2007-09-17 | 2011-01-18 | Industrial Technology Research Institute | Devices and methods for bit-level coding and decoding of turbo codes |
WO2011119137A1 (en) | 2010-03-22 | 2011-09-29 | Lrdc Systems, Llc | A method of identifying and protecting the integrity of a set of source data |
CN111272280B (zh) * | 2020-02-25 | 2020-12-15 | 电子科技大学 | 利用逆卷积提高光谱仪系统分辨率的方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4394642A (en) * | 1981-09-21 | 1983-07-19 | Sperry Corporation | Apparatus for interleaving and de-interleaving data |
FR2675971B1 (fr) * | 1991-04-23 | 1993-08-06 | France Telecom | Procede de codage correcteur d'erreurs a au moins deux codages convolutifs systematiques en parallele, procede de decodage iteratif, module de decodage et decodeur correspondants. |
FR2712760B1 (fr) * | 1993-11-19 | 1996-01-26 | France Telecom | Procédé pour transmettre des bits d'information en appliquant des codes en blocs concaténés. |
US6023783A (en) * | 1996-05-15 | 2000-02-08 | California Institute Of Technology | Hybrid concatenated codes and iterative decoding |
US5996104A (en) * | 1996-09-13 | 1999-11-30 | Herzberg; Hanan | System for coding system |
US5898698A (en) * | 1996-09-24 | 1999-04-27 | Orckit Communications Ltd. | Multiple codeword interleaver method and apparatus |
US6029264A (en) * | 1997-04-28 | 2000-02-22 | The Trustees Of Princeton University | System and method for error correcting a received data stream in a concatenated system |
EP1601109B1 (en) * | 1997-07-30 | 2010-04-21 | Samsung Electronics Co., Ltd. | Adaptive channel encoding method and device |
JP4033245B2 (ja) * | 1997-09-02 | 2008-01-16 | ソニー株式会社 | ターボ符号化装置およびターボ符号化方法 |
JP3515036B2 (ja) * | 1999-02-19 | 2004-04-05 | 株式会社エヌ・ティ・ティ・ドコモ | インターリービング方法、インターリービング装置、ターボ符号化方法及びターボ符号化装置 |
-
1999
- 1999-07-21 FR FR9909631A patent/FR2796780B1/fr not_active Expired - Fee Related
-
2000
- 2000-07-14 US US09/616,782 patent/US6782504B1/en not_active Expired - Lifetime
- 2000-07-19 WO PCT/FR2000/002080 patent/WO2001006661A1/fr active IP Right Grant
- 2000-07-19 EP EP00953266A patent/EP1205032B1/fr not_active Expired - Lifetime
- 2000-07-19 JP JP2001510997A patent/JP2004511114A/ja active Pending
- 2000-07-19 ES ES00953266T patent/ES2226898T3/es not_active Expired - Lifetime
- 2000-07-19 CN CN00813049.3A patent/CN1375130B/zh not_active Expired - Lifetime
- 2000-07-19 DE DE60014395T patent/DE60014395T2/de not_active Expired - Lifetime
- 2000-07-19 AU AU65783/00A patent/AU6578300A/en not_active Abandoned
- 2000-07-20 AR ARP000103733A patent/AR025211A1/es active IP Right Grant
-
2007
- 2007-06-21 JP JP2007164028A patent/JP4594963B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2004511114A (ja) | 2004-04-08 |
DE60014395D1 (de) | 2004-11-04 |
US6782504B1 (en) | 2004-08-24 |
FR2796780A1 (fr) | 2001-01-26 |
CN1375130A (zh) | 2002-10-16 |
ES2226898T3 (es) | 2005-04-01 |
JP2007318772A (ja) | 2007-12-06 |
AU6578300A (en) | 2001-02-05 |
EP1205032B1 (fr) | 2004-09-29 |
DE60014395T2 (de) | 2006-02-23 |
WO2001006661A1 (fr) | 2001-01-25 |
JP4594963B2 (ja) | 2010-12-08 |
EP1205032A1 (fr) | 2002-05-15 |
CN1375130B (zh) | 2010-05-12 |
FR2796780B1 (fr) | 2003-09-19 |
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