AR012214A1 - Accesorio para usar en un recipiente para expender liquidos y conjunto de recipiente usando el accesorio - Google Patents

Accesorio para usar en un recipiente para expender liquidos y conjunto de recipiente usando el accesorio

Info

Publication number
AR012214A1
AR012214A1 ARP980101456A ARP980101456A AR012214A1 AR 012214 A1 AR012214 A1 AR 012214A1 AR P980101456 A ARP980101456 A AR P980101456A AR P980101456 A ARP980101456 A AR P980101456A AR 012214 A1 AR012214 A1 AR 012214A1
Authority
AR
Argentina
Prior art keywords
container
accessory
neck
wall
fitting
Prior art date
Application number
ARP980101456A
Other languages
English (en)
Original Assignee
Graham Packaging Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Graham Packaging Corp filed Critical Graham Packaging Corp
Publication of AR012214A1 publication Critical patent/AR012214A1/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/1052—Bypassing or disabling error detection or correction

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Details Of Rigid Or Semi-Rigid Containers (AREA)

Abstract

Un accesorio (24) para usar en un recipiente destinado a expender líquidos. El accesorio (24) presenta un pico (26) y una funcion de retrodrenaje (32, 44)y está asegurado dentro del extremo del recipiente. El extremo del recipiente tiene un cuello(18) con un reborde (22) y un hombro (20). El accesorio (24)tiene una pared externa (30) con extremos superior e inferior (38, 40) y de forma frustoconica para asegurar que una porcion de pared externa (30) calcefriccionalmente el extremo delrec ipiente cuando el accesorio (24) es insertado en el extremo del recipiente, para impedir que el accesorio (24)sea insertado completamente a través del cuello (18) del recipiente. Un collar anular (34) se extiende hacia afuera desde lapare d externa (30) a unadistancia desde el extremo superior (36) de la pared externa (30), de manera que cuando el accesorio (24) se inserta en el cuello (18) del recipiente, elcollar (34) se coloca directamente debajo del hombro (20) del cuello(18). Se crean varias bandas de vinculacion entre el accesorio (24) y el cuello delrecipiente para asegurar una conexion sin pérdidas.
ARP980101456A 1997-04-04 1998-03-31 Accesorio para usar en un recipiente para expender liquidos y conjunto de recipiente usando el accesorio AR012214A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/833,371 US5896404A (en) 1997-04-04 1997-04-04 Programmable burst length DRAM

Publications (1)

Publication Number Publication Date
AR012214A1 true AR012214A1 (es) 2000-09-27

Family

ID=25264247

Family Applications (1)

Application Number Title Priority Date Filing Date
ARP980101456A AR012214A1 (es) 1997-04-04 1998-03-31 Accesorio para usar en un recipiente para expender liquidos y conjunto de recipiente usando el accesorio

Country Status (3)

Country Link
US (1) US5896404A (es)
JP (1) JP3714580B2 (es)
AR (1) AR012214A1 (es)

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US6721227B2 (en) * 2002-02-11 2004-04-13 Micron Technology, Inc. User selectable banks for DRAM
US7131033B1 (en) 2002-06-21 2006-10-31 Cypress Semiconductor Corp. Substrate configurable JTAG ID scheme
US7149824B2 (en) 2002-07-10 2006-12-12 Micron Technology, Inc. Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
US20040083334A1 (en) * 2002-10-28 2004-04-29 Sandisk Corporation Method and apparatus for managing the integrity of data in non-volatile memory system
JP4627411B2 (ja) * 2003-05-20 2011-02-09 ルネサスエレクトロニクス株式会社 メモリ装置及びメモリのエラー訂正方法
US7099221B2 (en) 2004-05-06 2006-08-29 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US20060010339A1 (en) * 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US7340668B2 (en) * 2004-06-25 2008-03-04 Micron Technology, Inc. Low power cost-effective ECC memory system and method
US7116602B2 (en) 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US6965537B1 (en) * 2004-08-31 2005-11-15 Micron Technology, Inc. Memory system and method using ECC to achieve low power refresh
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
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US7451380B2 (en) * 2005-03-03 2008-11-11 International Business Machines Corporation Method for implementing enhanced vertical ECC storage in a dynamic random access memory
US20060218467A1 (en) * 2005-03-24 2006-09-28 Sibigtroth James M Memory having a portion that can be switched between use as data and use as error correction code (ECC)
US7734985B2 (en) * 2006-02-27 2010-06-08 Intel Corporation Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode
JP2007257791A (ja) 2006-03-24 2007-10-04 Fujitsu Ltd 半導体記憶装置
US7774684B2 (en) * 2006-06-30 2010-08-10 Intel Corporation Reliability, availability, and serviceability in a memory device
US7894289B2 (en) * 2006-10-11 2011-02-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US7900120B2 (en) 2006-10-18 2011-03-01 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
US7865674B2 (en) * 2007-08-31 2011-01-04 International Business Machines Corporation System for enhancing the memory bandwidth available through a memory module
US7584308B2 (en) * 2007-08-31 2009-09-01 International Business Machines Corporation System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel
US7818497B2 (en) * 2007-08-31 2010-10-19 International Business Machines Corporation Buffered memory module supporting two independent memory channels
US8082482B2 (en) * 2007-08-31 2011-12-20 International Business Machines Corporation System for performing error correction operations in a memory hub device of a memory module
US7840748B2 (en) * 2007-08-31 2010-11-23 International Business Machines Corporation Buffered memory module with multiple memory device data interface ports supporting double the memory capacity
US7861014B2 (en) 2007-08-31 2010-12-28 International Business Machines Corporation System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel
US7899983B2 (en) 2007-08-31 2011-03-01 International Business Machines Corporation Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module
US8086936B2 (en) * 2007-08-31 2011-12-27 International Business Machines Corporation Performing error correction at a memory device level that is transparent to a memory channel
US8019919B2 (en) * 2007-09-05 2011-09-13 International Business Machines Corporation Method for enhancing the memory bandwidth available through a memory module
US7558887B2 (en) * 2007-09-05 2009-07-07 International Business Machines Corporation Method for supporting partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel
US7770077B2 (en) * 2008-01-24 2010-08-03 International Business Machines Corporation Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem
US7925824B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency
US8140936B2 (en) * 2008-01-24 2012-03-20 International Business Machines Corporation System for a combined error correction code and cyclic redundancy check code for a memory channel
US7930469B2 (en) 2008-01-24 2011-04-19 International Business Machines Corporation System to provide memory system power reduction without reducing overall memory system performance
US7925826B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency
US7930470B2 (en) * 2008-01-24 2011-04-19 International Business Machines Corporation System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller
US7925825B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to support a full asynchronous interface within a memory hub device
WO2009137157A1 (en) * 2008-03-31 2009-11-12 Rambus Inc. Independent threading of memory devices disposed on memory modules
US8910017B2 (en) 2012-07-02 2014-12-09 Sandisk Technologies Inc. Flash memory with random partition
CN103198020B (zh) * 2013-03-18 2016-05-25 山东华芯半导体有限公司 一种提高闪存使用寿命的方法
US9997233B1 (en) 2015-10-08 2018-06-12 Rambus Inc. Memory module with dynamic stripe width
KR102362229B1 (ko) 2017-08-10 2022-02-11 삼성전자주식회사 메모리 컨트롤러, 메모리 시스템 및 메모리 컨트롤러를 포함하는 어플리케이션 프로세서
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Also Published As

Publication number Publication date
US5896404A (en) 1999-04-20
JPH10283797A (ja) 1998-10-23
JP3714580B2 (ja) 2005-11-09

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Legal Events

Date Code Title Description
FA Abandonment or withdrawal