TW353797B - Method of shallow trench isolation - Google Patents

Method of shallow trench isolation

Info

Publication number
TW353797B
TW353797B TW086119851A TW86119851A TW353797B TW 353797 B TW353797 B TW 353797B TW 086119851 A TW086119851 A TW 086119851A TW 86119851 A TW86119851 A TW 86119851A TW 353797 B TW353797 B TW 353797B
Authority
TW
Taiwan
Prior art keywords
substrate
trench isolation
shallow trench
forming
insulation layer
Prior art date
Application number
TW086119851A
Other languages
English (en)
Inventor
Jian-Ting Lin
Heng-Sheng Huang
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW086119851A priority Critical patent/TW353797B/zh
Priority to US09/057,905 priority patent/US6057208A/en
Application granted granted Critical
Publication of TW353797B publication Critical patent/TW353797B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
TW086119851A 1997-12-27 1997-12-27 Method of shallow trench isolation TW353797B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW086119851A TW353797B (en) 1997-12-27 1997-12-27 Method of shallow trench isolation
US09/057,905 US6057208A (en) 1997-12-27 1998-04-09 Method of forming shallow trench isolation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW086119851A TW353797B (en) 1997-12-27 1997-12-27 Method of shallow trench isolation

Publications (1)

Publication Number Publication Date
TW353797B true TW353797B (en) 1999-03-01

Family

ID=21627491

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086119851A TW353797B (en) 1997-12-27 1997-12-27 Method of shallow trench isolation

Country Status (2)

Country Link
US (1) US6057208A (zh)
TW (1) TW353797B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100280107B1 (ko) * 1998-05-07 2001-03-02 윤종용 트렌치 격리 형성 방법
TW445577B (en) * 1998-06-22 2001-07-11 United Microelectronics Corp Manufacturing method of shallow trench isolation structure for avoiding the generation of microscratch on the surface of shallow trench isolation structure
TW406356B (en) * 1998-08-24 2000-09-21 United Microelectronics Corp A method of manufacturing shallow trench isolation structure
KR100292616B1 (ko) 1998-10-09 2001-07-12 윤종용 트렌치격리의제조방법
US6281081B1 (en) * 1998-11-13 2001-08-28 United Microelectronics Corp. Method of preventing current leakage around a shallow trench isolation structure
JP2002541664A (ja) * 1999-04-02 2002-12-03 シリコン ヴァレイ グループ サーマル システムズ リミテッド ライアビリティ カンパニー 側壁ライナー酸化成長前にトレンチ充填酸化物を付着させるためのトレンチ分離方法。
KR100338767B1 (ko) 1999-10-12 2002-05-30 윤종용 트렌치 소자분리 구조와 이를 갖는 반도체 소자 및 트렌치 소자분리 방법
JP3604072B2 (ja) * 1999-11-08 2004-12-22 沖電気工業株式会社 半導体装置の製造方法
US7125783B2 (en) 2001-04-18 2006-10-24 Integrated Device Technology, Inc. Dielectric anti-reflective coating surface treatment to prevent defect generation in associated wet clean
US6455382B1 (en) 2001-05-03 2002-09-24 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-step method for forming sacrificial silicon oxide layer
US6919259B2 (en) * 2002-10-21 2005-07-19 Taiwan Semiconductor Manufacturing Co., Ltd Method for STI etching using endpoint detection
US7507521B2 (en) * 2004-08-09 2009-03-24 Intel Corporation Silicon based optically degraded arc for lithographic patterning
US7687225B2 (en) * 2004-09-29 2010-03-30 Intel Corporation Optical coatings
US9101954B2 (en) * 2013-09-17 2015-08-11 Applied Materials, Inc. Geometries and patterns for surface texturing to increase deposition retention

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5433794A (en) * 1992-12-10 1995-07-18 Micron Technology, Inc. Spacers used to form isolation trenches with improved corners
US5316965A (en) * 1993-07-29 1994-05-31 Digital Equipment Corporation Method of decreasing the field oxide etch rate in isolation technology
KR100216267B1 (ko) * 1996-12-26 1999-08-16 구본준 트렌치 격리구조를 갖는 반도체 장치 제조방법
US5728621A (en) * 1997-04-28 1998-03-17 Chartered Semiconductor Manufacturing Pte Ltd Method for shallow trench isolation

Also Published As

Publication number Publication date
US6057208A (en) 2000-05-02

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees